TAS-MRAM based Non-volatile FPGA logic circuit. - Weisheng Zhao; Eric Belhaire; Bernard Dieny; Guillaume Prenat; Claude Chappert (FPT, 2007)

Synthesis of Finite State Machines with Magnetic Domain Wall Logic. - Jacques-Olivier Klein; Eric Belhaire; Claude Chappert; Florent Ouchet; Russell Cowburn; Dan Read; Dorothee Petit (ISCAS, 2007)

Injection locked CMOS buffer dedicated to nanomagnetic based voltage controlled oscillator. - Franck Badets; Lieven Lagae; Sven Cornelissen; Thibaut Devolder; Claude Chappert (ICECS, 2008)

Spintronic Device Based Non-volatile Low Standby Power SRAM. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Pascale Mazoyer (ISVLSI, 2008)

Spin transfer torque (STT)-MRAM-based runtime reconfiguration FPGA circuit. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Pascale Mazoyer (ACM Trans. Embed. Comput. Syst., 2009)

TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. - Weisheng Zhao; Eric Belhaire; Claude Chappert; Bernard Dieny; Guillaume Prenat (ACM Trans. Reconfigurable Technol. Syst., 2009)

High Density Asynchronous LUT Based on Non-volatile MRAM Technology. - Sumanta Chaudhuri; Weisheng Zhao; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (FPL, 2010)

Design of embedded MRAM macros for memory-in-logic applications. - Sumanta Chaudhuri; Weisheng Zhao; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (ACM Great Lakes Symposium on VLSI, 2010)

Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power. - Yahya Lakys; Weisheng Zhao; Jacques-Olivier Klein; Claude Chappert (ARC, 2011)

Design of MRAM based logic circuits and its applications. - Weisheng Zhao; Lionel Torres; Yoann Guillemenet; Luis Vitório Cargnini; Yahya Lakys; Jacques-Olivier Klein; Dafine Ravelosona; Gilles Sassatelli; Claude Chappert (ACM Great Lakes Symposium on VLSI, 2011)

High Performance SoC Design Using Magnetic Logic and Memory. - Weisheng Zhao; Lionel Torres; Luis Vitório Cargnini; Raphael Martins Brum; Yue Zhang 010; Yoann Guillemenet; Gilles Sassatelli; Yahya Lakys; Jacques-Olivier Klein; Daniel Etiemble; Dafine Ravelosona; Claude Chappert (VLSI-SoC (Selected Papers), 2011)

Embedded MRAM for high-speed computing. - Weisheng Zhao; Yue Zhang 010; Yahya Lakys; Jacques-Olivier Klein; Daniel Etiemble; D. Revelosona; Claude Chappert; Lionel Torres; Luis Vitório Cargnini; Raphael Martins Brum; Yoann Guillemenet; Gilles Sassatelli (VLSI-SoC, 2011)

Design considerations and strategies for high-reliable STT-MRAM. - Weisheng Zhao; Thibaut Devolder; Yahya Lakys; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (Microelectron. Reliab., 2011)

MRAM crossbar based configurable logic block. - Yahya Lakys; Weisheng Zhao; Jacques-Olivier Klein; Claude Chappert (ISCAS, 2012)

Nanodevice-based novel computing paradigms and the neuromorphic approach. - Weisheng Zhao; Damien Querlioz; Jacques-Olivier Klein; Djaafar Chabi; Claude Chappert (ISCAS, 2012)

Crossbar architecture based on 2R complementary resistive switching memory cell. - Weisheng Zhao; Yue Zhang 010; Jacques-Olivier Klein; Damien Querlioz; Djaafar Chabi; Dafine Ravelosona; Claude Chappert; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller (NANOARCH, 2012)

Cross-point architecture for spin transfer torque magnetic random access memory - Weisheng Zhao; Sumanta Chaudhuri; Celso Accoto; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (CoRR, 2012)

Failure and reliability analysis of STT-MRAM. - Weisheng Zhao; Yue Zhang 010; Thibaut Devolder; Jacques-Olivier Klein; Dafine Ravelosona; Claude Chappert; Pascale Mazoyer (Microelectron. Reliab., 2012)

Analytical study of complementary memristive synchronous logic gates. - Jean-Michel Portal; Mathieu Moreau; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; et al. (NANOARCH, 2013)

Low power magnetic flip-flop based on checkpointing and self-enable mechanism. - Djaafar Chabi; Weisheng Zhao; Yue Zhang 010; Jacques-Olivier Klein; Claude Chappert (NEWCAS, 2013)

Synchronous full-adder based on complementary resistive switching memory cells. - Yue Zhang 010; Erya Deng; Jacques-Olivier Klein; Damien Querlioz; Dafine Ravelosona; Claude Chappert; Weisheng Zhao; Mathieu Moreau; Jean-Michel Portal; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; et al. (NEWCAS, 2013)

Emerging hybrid logic circuits based on non-volatile magnetic memories. - Weisheng Zhao; Guillaume Prenat; Jacques-Olivier Klein; Bernard Dieny; Claude Chappert; Dafine Ravelosona (NEWCAS, 2013)

Spin-electronics based logic fabrics. - Weisheng Zhao; Jacques-Olivier Klein; Zhaohao Wang; Yue Zhang 010; Nesrine Ben Romdhane; Damien Querlioz; Dafine Ravelosona; Claude Chappert (VLSI-SoC, 2013)

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. - Wang Kang 001; Weisheng Zhao; Zhaohao Wang; Yue Zhang 010; Jacques-Olivier Klein; Youguang Zhang; Claude Chappert; Dafine Ravelosona (Microelectron. Reliab., 2013)

Magnetic Adder Based on Racetrack Memory. - Hong-Phuc Trinh; Weisheng Zhao; Jacques-Olivier Klein; Yue Zhang 010; Dafine Ravelosona; Claude Chappert (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

An overview of spin-based integrated circuits. - Wang Kang 001; Weisheng Zhao; Zhaohao Wang; Jacques-Olivier Klein; Yue Zhang 010; Djaafar Chabi; Youguang Zhang; Dafine Ravelosona; Claude Chappert (ASP-DAC, 2014)

Spintronics for low-power computing. - Yue Zhang 010; Weisheng Zhao; Jacques-Olivier Klein; Wang Kang 001; Damien Querlioz; Youguang Zhang; Dafine Ravelosona; Claude Chappert (DATE, 2014)

Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. - Zhaohao Wang; Weisheng Zhao; Wang Kang 001; Youguang Zhang; Jacques-Olivier Klein; Claude Chappert (IJCNN, 2014)

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. - Weisheng Zhao; Jean-Michel Portal; Wang Kang 001; Mathieu Moreau; Yue Zhang 010; Hassen Aziza; Jacques-Olivier Klein; Zhaohao Wang; Damien Querlioz; Damien Deleruyelle; Marc Bocquet; Dafine Ravelosona; et al. (J. Parallel Distributed Comput., 2014)

Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms. - Djaafar Chabi; Weisheng Zhao; Erya Deng; Yue Zhang 010; Nesrine Ben Romdhane; Jacques-Olivier Klein; Claude Chappert (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories. - Weisheng Zhao; Mathieu Moreau; Erya Deng; Yue Zhang 010; Jean-Michel Portal; Jacques-Olivier Klein; Marc Bocquet; Hassen Aziza; Damien Deleruyelle; Christophe Muller; Damien Querlioz; Nesrine Ben Romdhane; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. - Wang Kang 001; Liuyang Zhang; Weisheng Zhao; Jacques-Olivier Klein; Youguang Zhang; Dafine Ravelosona; Claude Chappert (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. - Wang Kang 001; Yue Zhang 010; Zhaohao Wang; Jacques-Olivier Klein; Claude Chappert; Dafine Ravelosona; Gefei Wang; Youguang Zhang; Weisheng Zhao (ACM J. Emerg. Technol. Comput. Syst., 2015)