Overview of complementary GaAs technology for high-speed VLSI circuits. - Richard B. Brown; Bruce Bernhardt; M. LaMacchia; J. Abrokwah; Phiroze N. Parakh; Todd D. Basso; Spencer M. Gold; S. Stetson; Claude R. Gauthier; D. Foster; B. Crawforth; T. McQuire; et al. (IEEE Trans. Very Large Scale Integr. Syst., 1998)

CGaAs PowerPC FXU. - Alan J. Drake; Todd D. Basso; Spencer M. Gold; Keith L. Kraver; Phiroze N. Parakh; Claude R. Gauthier; P. Sean Stetson; Richard B. Brown (DAC, 2000)

Dynamic Receiver Biasing For Inter-Chip Communication. - Claude R. Gauthier; Jayakumaran Sivagnaname; Richard B. Brown (ARVLSI, 2001)

Macro-modeling concepts for the chip electrical interface. - Brian W. Amick; Claude R. Gauthier; Dean Liu (DAC, 2002)

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. - Socrates D. Vamvakos; Bendik Kleveland; Dipak K. Sikdar; B. K. Ahuja; Haidang Lin; Jayaprakash Balachandran; Wignes Balakrishnan; Aldo Bottelli; Jawji Chen; Xiaole Chen; Jae Choi; Jeong Choi; et al. (ESSCIRC, 2012)

A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications. - Socrates D. Vamvakos; Claude R. Gauthier; Chethan Rao; Karthisha Ramoshan Canagasaby; Prashant Choudhary; Sanjay Dabral; Shaishav Desai; Mahmudul Hassan; Kuo-Chiang Hsieh; Bendik Kleveland; Gurupada Mandal; Richard Rouse; et al. (MWSCAS, 2012)

TDD-based Asymmetrical Ethernet Physical Layer for Automotive Applications. - Kamal Dalmia; Claude R. Gauthier (ISCAS, 2022)