Impact of reconfiguration logic on the optimization of defect-tolerant integrated circuits. - Claude Thibeault; Jean-Louis Houle (FTCS, 1990)

Test quality of hierarchical defect-tolerant integrated circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (J. Electron. Test., 1992)

Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (J. Circuits Syst. Comput., 1992)

Some Results on Yield and Local Design Rule Relaxation. - J. Crépeau; Claude Thibeault; Yvon Savaria (DFT, 1993)

Using Fourier Analysis to Enhance IC Testability. - Claude Thibeault (DFT, 1994)

A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (IEEE Trans. Computers, 1994)

FFT-based test of a yield monitor circuit. - Claude Thibeault; A. Payeur (DFT, 1995)

Detection and location of faults and defects using digital signal processing. - Claude Thibeault (VTS, 1995)

Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits. - Claude Thibeault; Yvon Savaria; Jean-Louis Houle (IEEE Trans. Computers, 1995)

Experimental Results from Iddf Testing. - Claude Thibeault; A. Payeur (DFT, 1996)

Panel Summaries. - Yervant Zorian; Tom Anderson; Yvon Savaria; Claude Thibeault; André Ivanov (IEEE Des. Test Comput., 1996)

Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. - Yves Gagnon; Yvon Savaria; Michel Meunier; Claude Thibeault (DFT, 1997)

A Cost Model for VLSI / MCM Systems. - Michel Kafrouni; Claude Thibeault; Yvon Savaria (DFT, 1997)

A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. - Claude Thibeault (VTS, 1997)

Increasing Current Testing Resolution. - Claude Thibeault (DFT, 1998)

On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis. - Claude Thibeault; Luc Boisvert (DFT, 1998)

Diagnosis method based on ΔIddq probabilistic signatures: experimental results. - Claude Thibeault; Luc Boisvert (ITC, 1998)

An histogram based procedure for current testing of active defects. - Claude Thibeault (ITC, 1999)

On the Comparison of IDDQ and IDDQ Testing. - Claude Thibeault (VTS, 1999)

A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations. - Claude Thibeault; Guy Bégin (IEEE Trans. Computers, 1999)

Improving Delta-I_DDQ-based test methods. - Claude Thibeault (ITC, 2000)

Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi Algorithm. - Claude Thibeault (VTS, 2000)

Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results. - Claude Thibeault (J. Electron. Test., 2000)

On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults. - Claude Thibeault (IEEE Trans. Computers, 2000)

Tools for the Characterization of Bipolar CML Testability. - Ginette Monté; Bernard Antaki; Serge Patenaude; Yvon Savaria; Claude Thibeault; Pieter M. Trouborst (VTS, 2001)

Yield Modeling of a WSI Telecom Router Architecture. - Bing Qiu 003; Yvon Savaria; Meng Lu; Chunyan Wang 004; Claude Thibeault (DFT, 2002)

Speeding-Up IDDQ Measurements. - Claude Thibeault (VTS, 2002)

3DSDM: A 3 Data-Source Diagnostic Method. - Yassine Hariri; Claude Thibeault (DFT, 2003)

Replacing IDDQ Testing: With Variance Reduction. - Claude Thibeault (J. Electron. Test., 2003)

On Faster IDDQ Measurements. - Claude Thibeault (J. Electron. Test., 2003)

On New Current Signatures and Adaptive Test Technique Combination. - Claude Thibeault (VTS, 2004)

On a New Outlier Rejection Technique. - Claude Thibeault (VTS, 2007)

Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors. - Yassine Hariri; Claude Thibeault (IET Comput. Digit. Tech., 2007)

From synchronous to GALS: A new architecture for FPGAs. - René Gagné; Jean Belzile; Claude Thibeault (Microelectron. J., 2009)

Testing for Parasitic Memory Effect in SRAMs. - Sandra Irobi; Zaid Al-Ars; Said Hamdioui; Claude Thibeault (Asian Test Symposium, 2011)

Low complexity low power non-recursive digital filters with unconstrained topology. - Marc Joliveau; Michel Gendreau; François Gagnon; Claude Thibeault (ECCTD, 2011)

Leveraging green communications for carbon emission reductions: Techniques, testbeds, and emerging carbon footprint standards. - Charles L. Despins; Fabrice Labeau; Tho Le-Ngoc; Richard Labelle; Mohamed Cheriet; Claude Thibeault; François Gagnon; Alberto Leon-Garcia; Omar Cherkaoui; Bill St. Arnaud; Jacques Mcneill; Yves Lemieux; et al. (IEEE Commun. Mag., 2011)

CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation. - Claude Thibeault; Yassine Hariri (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Fault tolerant flight control system using emmae method and reconfiguration with sliding mode technique. - Azeddine Ghodbane; Maarouf Saad; Jean-François Boland; Claude Thibeault (CCECE, 2012)

High-throughput LDPC decoding using the RHS algorithm. - François Leduc-Primeau; Alexandre J. Raymond; Pascal Giard; Kevin Cushon; Claude Thibeault; Warren J. Gross (DASIP, 2012)

FPGA implementation and evaluation of discrete-time chaotic generators circuits. - Pascal Giard; Georges Kaddoum; François Gagnon; Claude Thibeault (IECON, 2012)

An LPI design for secure OFDM systems. - Marwen Bouanen; François Gagnon; Georges Kaddoum; Denis Couillard; Claude Thibeault (MILCOM, 2012)

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors. - Claude Thibeault; Yassine Hariri; Christelle Hobeika (J. Electron. Test., 2012)

Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria; Claude Thibeault (FTSCS, 2013)

Multi-user Multi-Carrier Differential Chaos Shift Keying communication system. - Georges Kaddoum; Francois-Dominique Richardson; Sarra Adouni; François Gagnon; Claude Thibeault (IWCMC, 2013)

A 0.35∼6.25 GHz cognitive radio frequency synthesizer architecture. - Zakaria El Alaoui Ismaili; Frederic Nabki; Wessam Ajib; Claude Thibeault (MWSCAS, 2013)

A methodology for system-level fault injection based on gate-level faulty behavior. - R. Robache; Jean-François Boland; Claude Thibeault; Yvon Savaria (NEWCAS, 2013)

A Fast Software Polar Decoder. - Pascal Giard; Gabi Sarkis; Claude Thibeault; Warren J. Gross (CoRR, 2013)

Technical report: Functional Constraint Extraction From Register Transfer Level for ATPG. - Christelle Hobeika; Claude Thibeault; Jean-François Boland (CoRR, 2013)

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design. - Claude Thibeault; Yassine Hariri; Syed Rafay Hasan; Christelle Hobeika; Yvon Savaria; Yves Audet; Fatima Zahra Tazi (J. Electron. Test., 2013)

Autogenerating software polar decoders. - Gabi Sarkis; Pascal Giard; Claude Thibeault; Warren J. Gross (GlobalSIP, 2014)

Fast software polar decoders. - Pascal Giard; Gabi Sarkis; Claude Thibeault; Warren J. Gross (ICASSP, 2014)

Multi-abstraction level signature generation and comparison based on radiation single event upset. - Christelle Hobeika; Simon Pichette; M. A. Leonard; Claude Thibeault; Jean-François Boland; Yves Audet (IOLTS, 2014)

Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. - Khaza Anuarul Hoque; Otmane Aït Mohamed; Yvon Savaria; Claude Thibeault (MEMOCODE, 2014)

Increasing the speed of polar list decoders. - Gabi Sarkis; Pascal Giard; Alexander Vardy; Claude Thibeault; Warren J. Gross (SiPS, 2014)

A 237 Gbps Unrolled Hardware Polar Decoder. - Pascal Giard; Gabi Sarkis; Claude Thibeault; Warren J. Gross (CoRR, 2014)

On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations. - Fatima Zahra Tazi; Claude Thibeault; Yvon Savaria; Simon Pichette; Yves Audet (CoRR, 2014)

Fast Polar Decoders: Algorithm and Implementation. - Gabi Sarkis; Pascal Giard; Alexander Vardy; Claude Thibeault; Warren J. Gross (IEEE J. Sel. Areas Commun., 2014)

A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline. - Louis-Charles Trudeau; Ghyslain Gagnon; François Gagnon; Claude Thibeault; Thomas Awad; Doug Morrissey (ASYNC, 2015)

An automated fault injection for evaluation of LUTs robustness in SRAM-based FPGAs. - Anis Souari; Claude Thibeault; Yves Blaquière; Raoul Velazco (EWDTS, 2015)

Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis. - Anis Souari; Claude Thibeault; Yves Blaquière; Raoul Velazco (IOLTS, 2015)

Self-timed circuits FPGA implementation flow. - Mickaël Fiorentino; Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (NEWCAS, 2015)

A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs. - Pascal Giard; Gabi Sarkis; Claude Thibeault; Warren J. Gross (SiPS, 2015)

Foreword. - Claude Thibeault (VTS, 2015)

Circuit Level Modeling of Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiation. - Mostafa Darvishi; Yves Audet; Yves Blaquière; Claude Thibeault (CoRR, 2015)

Unrolled Polar Decoders, Part I: Hardware Architectures. - Pascal Giard; Gabi Sarkis; Claude Thibeault; Warren J. Gross (CoRR, 2015)

Unrolled Polar Decoders, Part II: Fast List Decoders. - Gabi Sarkis; Pascal Giard; Alexander Vardy; Claude Thibeault; Warren J. Gross (CoRR, 2015)

Functional Constraint Extraction From Register Transfer Level for ATPG. - Christelle Hobeika; Claude Thibeault; Jean-François Boland (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Efficient identification of Faces in video Streams using low-Power Multi-Core Devices. - Donavan Prieur; Eric Granger; Yvon Savaria; Claude Thibeault (Handbook of Pattern Recognition and Computer Vision, 2016)

A multi-Gbps unrolled hardware list decoder for a systematic polar code. - Pascal Giard; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Andreas Peter Burg; Claude Thibeault; Warren J. Gross (ACSSC, 2016)

Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA. - Fatima Zahra Tazi; Claude Thibeault; Yvon Savaria (CCECE, 2016)

Partitioned successive-cancellation list decoding of polar codes. - Seyyed Ali Hashemi; Alexios Balatsoukas-Stimming; Pascal Giard; Claude Thibeault; Warren J. Gross (ICASSP, 2016)

A practical design method for prototyping self-timed processors using FPGAs. - Mickaël Fiorentino; Yvon Savaria; Claude Thibeault; Pascal Gervais (ISCAS, 2016)

Hardware decoders for polar codes: An overview. - Pascal Giard; Gabi Sarkis; Alexios Balatsoukas-Stimming; YouZhe Fan; Chi-Ying Tsui; Andreas Peter Burg; Claude Thibeault; Warren J. Gross (ISCAS, 2016)

WeSPer: A flexible small delay defect quality metric. - Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (VTS, 2016)

Fast List Decoders for Polar Codes. - Gabi Sarkis; Pascal Giard; Alexander Vardy; Claude Thibeault; Warren J. Gross (IEEE J. Sel. Areas Commun., 2016)

Towards an efficient SEU effects emulation on SRAM-based FPGAs. - Anis Souari; Claude Thibeault; Yves Blaquière; Raoul Velazco (Microelectron. Reliab., 2016)

Design of a tolerant flight control system in response to multiple actuator control signal faults induced by cosmic rays. - Azeddine Ghodbane; Maarouf Saad; Christelle Hobeika; Jean-François Boland; Claude Thibeault (IEEE Trans. Aerosp. Electron. Syst., 2016)

Multi-Mode Unrolled Architectures for Polar Decoders. - Pascal Giard; Gabi Sarkis; Claude Thibeault; Warren J. Gross (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. - Gabi Sarkis; Ido Tal; Pascal Giard; Alexander Vardy; Claude Thibeault; Warren J. Gross (IEEE Trans. Commun., 2016)

High-Speed Decoders for Polar Codes - Pascal Giard; Claude Thibeault; Warren J. Gross (Springer, 2017)

FPGA implementation of Token-based Self-timed processors: A case study. - Mickaël Fiorentino; Yvon Savaria; Claude Thibeault (NEWCAS, 2017)

A new delay testing signal scheme robust to power distribution network impedance variation. - Claude Thibeault; Ali Louati (VTS, 2017)

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. - Pascal Giard; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Andrea Bonetti; Claude Thibeault; Warren J. Gross; Philippe Flatresse; Andreas Burg 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. - Omar Al-Terkawi Hasib; Daniel Crepeau; Thomas Awad; Andrei Dulipovici; Yvon Savaria; Claude Thibeault (VTS, 2018)

On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques. - Claude Thibeault; Ghyslain Gagnon (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Fast Low-Complexity Decoders for Low-Rate Polar Codes. - Pascal Giard; Alexios Balatsoukas-Stimming; Gabi Sarkis; Claude Thibeault; Warren J. Gross (J. Signal Process. Syst., 2018)

Low-Latency Software Polar Decoders. - Pascal Giard; Gabi Sarkis; Camille Leroux; Claude Thibeault; Warren J. Gross (J. Signal Process. Syst., 2018)

AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology. - Mickaël Fiorentino; Claude Thibeault; Yvon Savaria; François Gagnon; Tom Awad; Doug Morrissey; Michel Laurence (ASYNC, 2019)

A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits. - Maryem Benyoussef; Claude Thibeault; Yvon Savaria (ISCAS, 2019)

Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. - Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (J. Electron. Test., 2019)

Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. - Omar Al-Terkawi Hasib; Yvon Savaria; Claude Thibeault (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Introducing KeyRing self-timed microarchitecture and timing-driven design flow. - Mickaël Fiorentino; Claude Thibeault; Yvon Savaria (IET Comput. Digit. Tech., 2021)

Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation. - Simon Pichette; Claude Thibeault (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)