Leakage Power Analysis of Multi-bit Adders Using Transistor Gate Length Increase. - Savithra Eratne; Claudia Romo; Eugene John (CDES, 2010)

Leakage and Access Time Tradeoffs for Cache in High Performance Microprocessors. - Savithra Eratne; Claudia Romo; Eugene John; Byeong Kil Lee (CDES, 2010)