A design methodology for the correct specification of VLSI systems. - Cristiana Bolchini; Massimo Bombana; Patrizia Cavalloro; Claudio Costi; Franco Fummi; Giuseppe Zaza (Microprocess. Microprogramming, 1993)

From Behavioral Description to Systolic Array Based Architectures. - Alessandro Balboni; Claudio Costi; Franco Fummi; Donatella Sciuto (EDAC-ETC-EUROASIC, 1994)

Automatic clock tree generation in ASIC designs. - Alessandro Balboni; Claudio Costi; A. Pellencin; M. Quadrini; Donatella Sciuto (ED&TC, 1995)

A new DFT methodology for sequential circuits. - Claudio Costi; Micaela Serra; Donatella Sciuto (J. Electron. Test., 1995)

Clock skew reduction in ASIC logic design: a methodology for clock tree management. - Alessandro Balboni; Claudio Costi; Massimo Pellencin; Andrea Quadrini; Donatella Sciuto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A methodology for analyzing hardware description language specifications of legacy designs. - Claudio Costi (2001)