A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder. - Thaísa Leal da Silva; Cláudio Machado Diniz; João Alberto Vortmann; Luciano Volcan Agostini; Altamiro Amadeu Susin; Sergio Bampi (PSIVT, 2007)

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video. - Cláudio Machado Diniz; Bruno Zatt; Luciano Volcan Agostini; Altamiro Amadeu Susin; Sergio Bampi (ICME, 2009)

Homogeneity and distortion-based intra mode decision architecture for H.264/AVC. - Guilherme Corrêa 001; Cláudio Machado Diniz; Sergio Bampi; Daniel Palomino 001; Roger Endrigo Carvalho Porto; Luciano Volcan Agostini (ICECS, 2010)

Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors. - Cláudio Machado Diniz; João S. Altermann; Eduardo A. C. da Costa; Sergio Bampi (SBCCI, 2010)

Timing and interface communication analysis of H.264/AVC encoder using SystemC model. - Bruno Zatt; Cláudio Machado Diniz; Luciano Volcan Agostini; Sergio Bampi (VLSI-SoC, 2010)

SHBS: A heuristic for fast inter mode decision of H.264/AVC standard targeting VLSI design. - Guilherme Corrêa 001; Daniel Palomino 001; Cláudio Machado Diniz; Luciano Volcan Agostini; Sergio Bampi (ICME, 2011)

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p. - Cláudio Machado Diniz; Bruno Zatt; Cristiano Thiele; Altamiro Amadeu Susin; Sergio Bampi; Felipe Sampaio; Daniel Palomino 001; Luciano Volcan Agostini (ISCAS, 2011)

Applying CUDA Architecture to Accelerate Full Search Block Matching Algorithm for High Performance Motion Estimation in Video Encoding. - Eduarda Monteiro; Bruno Boessio Vizzotto; Cláudio Machado Diniz; Bruno Zatt; Sergio Bampi (SBAC-PAD, 2011)

Real-time block matching motion estimation onto GPGPU. - Eduarda Monteiro; Marilena Maule; Felipe Sampaio; Cláudio Machado Diniz; Bruno Zatt; Sergio Bampi (ICIP, 2012)

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders. - Daniel Palomino 001; Guilherme Corrêa 001; Cláudio Machado Diniz; Sergio Bampi; Luciano Volcan Agostini; Altamiro Amadeu Susin (Int. J. Reconfigurable Comput., 2012)

Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder. - Guilherme Corrêa 001; Daniel Palomino 001; Cláudio Machado Diniz; Sergio Bampi; Luciano Volcan Agostini (VLSI Design, 2012)

High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC. - Cláudio Machado Diniz; Muhammad Shafique 001; Sergio Bampi; Jörg Henkel (ICIP, 2013)

Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures. - Cláudio Machado Diniz; Muhammad Shafique 001; Sergio Bampi; Jörg Henkel (FPL, 2014)

Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms. - Eduarda Monteiro; Bruno Boessio Vizzotto; Cláudio Machado Diniz; Marilena Maule; Bruno Zatt; Sergio Bampi (Int. J. Parallel Program., 2014)

A deblocking filter hardware architecture for the high efficiency video coding standard. - Cláudio Machado Diniz; Muhammad Shafique 001; Felipe Vogel Dalcin; Sergio Bampi; Jörg Henkel (DATE, 2015)

SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder. - Bianca Silveira; Cláudio Machado Diniz; Mateus Fonseca; Eduardo A. C. da Costa (ICECS, 2015)

Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors. - Cláudio Machado Diniz; Mateus Beck Fonseca; Eduardo A. C. da Costa; Sergio Bampi (NEWCAS, 2015)

A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding. - Cláudio Machado Diniz; Muhammad Shafique 001; Sergio Bampi; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Power-efficient sum of absolute differences architecture using adder compressors. - Bianca Silveira; Guilherme Paim; Cláudio Machado Diniz; Eduardo A. C. da Costa (ICECS, 2016)

Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding. - Giovani Malossi; Daniel Palomino 001; Cláudio Machado Diniz; Altamiro Amadeu Susin; Sergio Bampi (NEWCAS, 2016)

A novel pruned-based algorithm for energy-efficient SATD operation in the HEVC coding. - Leonardo Bandeira Soares; Cláudio Machado Diniz; Eduardo Antonio Cesar da Costa; Sergio Bampi (SBCCI, 2016)

Exploiting absolute arithmetic for power-efficient sum of absolute differences. - Brunno Abreu; Guilherme Paim; Mateus Grellert; Bianca Silveira; Cláudio Machado Diniz; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Exploring the use of parallel prefix adder topologies into approximate adder circuits. - Morgana Macedo; Leonardo Bandeira Soares; Bianca Silveira; Cláudio Machado Diniz; Eduardo A. C. da Costa (ICECS, 2017)

Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding. - Bianca Silveira; Brunno Abreu; Guilherme Paim; Mateus Grellert; Rafael S. Ferreira; Cláudio Machado Diniz; Eduardo Costa 001; Sergio Bampi (ICECS, 2017)

Low power sum of absolute differences architecture using novel hybrid adder. - Rafael Ferreira 001; Bianca Silveira; Mateus Beck Fonseca; Cláudio Machado Diniz; Eduardo A. C. da Costa (LASCAS, 2017)

Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors. - Bianca Silveira; Rafael S. Ferreira; Guilherme Paim; Cláudio Machado Diniz; Eduardo A. C. da Costa (NEWCAS, 2017)

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design. - Bianca Silveira; Guilherme Paim; Brunno Abreu; Mateus Grellert; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Energy-based voice activity detection algorithm using Gaussian and Cauchy kernels. - Aminadabe dos Santos Pires Soares; Wemerson Delcio Parreira; Everton Granemann Souza; Sérgio Jose Melo de Almeida; Cláudio Machado Diniz; Chiara das Dores do Nascimento; Matheus F. Stigger (LASCAS, 2018)

Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering. - Leonardo Bandeira Soares; Morgana M. A. da Rosa; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (LASCAS, 2018)

Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators. - Rafael Ferreira 001; Mateus Leme; Marcel Moscarelli Corrêa; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (ICECS, 2019)

Approximate Sum of Absolute Transformed Differences Hardware Accelerator. - Matheus F. Stigger; Victor H. S. Lima; Leonardo Bandeira Soares; Cláudio Machado Diniz; Sergio Bampi (ICECS, 2019)

HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators. - Rafael S. Ferreira; Guilherme Paim; Brunno A. Abreu; Cláudio Machado Diniz; Eduardo A. C. da Costa; Sergio Bampi (MWSCAS, 2019)

Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators. - Leonardo Bandeira Soares; Morgana Macedo Azevedo da Rosa; Cláudio Machado Diniz; Eduardo Antonio Cesar da Costa; Sergio Bampi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard. - Daiane Freitas; Rafael da Silva; Ícaro Siqueira; Cláudio Machado Diniz; Ricardo A. L. Reis; Mateus Grellert (EUSIPCO, 2020)

Approximate SATD Hardware Accelerator Using the 8 × 8 Hadamard Transform. - Matheus F. Stigger; Victor H. S. Lima; Leonardo Bandeira Soares; Cláudio Machado Diniz; Sergio Bampi (LASCAS, 2020)

VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis. - Rafael S. Ferreira; Lucas Santos; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (ICECS 2022, 2022)

Improving Content-Aware Video Streaming in Congested Networks with In-Network Computing. - Leonardo Gobatto; Mateus Saquetti; Cláudio Machado Diniz; Bruno Zatt; Weverton Cordeiro; José Rodrigo Azambuja (ISCAS, 2022)

Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding. - Bianca Silveira; Luiz Neto; Daniel Palomino 001; Cláudio Machado Diniz; Guilherme Corrêa 001 (ISCAS, 2022)

High-Throughput Multifilter VLSI Design for the AV1 Fractional Motion Estimation. - Daiane Freitas; Bruna Nagai; Mateus Grellert; Cláudio Machado Diniz; Guilherme Corrêa 001 (SBCCI, 2022)

The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures. - Bianca Silveira; Guilherme Paim; Brunno Alves Abreu; Rafael dos Santos Ferreira; Cláudio Machado Diniz; Eduardo Antônio César da Costa; Sergio Bampi (Circuits Syst. Signal Process., 2022)

Guest Editors' Introduction: SBCCI 2021. - Cláudio Machado Diniz; Bruno Zatt (IEEE Des. Test, 2022)

Multiversion Low-Power Hardware Accelerator for the AV1 Interpolation Filters. - Daiane Freitas; Mateus Grellert; Cláudio Machado Diniz; Guilherme Corrêa 001 (ISCAS, 2023)

Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder. - Bruna Garcia; Bianca Silveira; Cláudio Machado Diniz; Daniel Palomino 001; Guilherme Corrêa 001 (LASCAS, 2023)

Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding. - Rafael S. Ferreira; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (SBCCI, 2023)

A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard. - Bianca Silveira; Daniel Palomino 001; Cláudio Machado Diniz; Guilherme Corrêa 001 (SBCCI, 2023)

Improving Video Streaming Quality in Congested Networks with In-Network Computing. - Leonardo Gobatto; Mateus Saquetti; Cláudio Machado Diniz; Bruno Zatt; Weverton Cordeiro; José Rodrigo Azambuja (LASCAS, 2024)

Energy-Efficient Hardware Architecture for VVC TZS Using Approximate Subtractors. - Rafael Ferreira 001; Luciano Agostini; Cláudio Machado Diniz; Bruno Zatt (LASCAS, 2025)

Low-Power Multiversion Interpolation Filter Accelerator With Hardware Reuse for AV1 Codec. - Daiane Freitas; Patrick Rosa; Leonardo Müller; Daniel Palomino 001; Cláudio Machado Diniz; Mateus Grellert; Guilherme Corrêa 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)