Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. - Pierluigi Nuzzo; Claudio Nani; Sergio Saponara; Luca Fanucci; Geert Van der Plas (DATE, 2008)

Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters. - Sergio Saponara; Pierluigi Nuzzo; Claudio Nani; Geert Van der Plas; Luca Fanucci (IEICE Trans. Electron., 2009)

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. - Konstantinos Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (ISSCC, 2011)

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. - Kostas Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (IEEE J. Solid State Circuits, 2011)

A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. - Pierluigi Nuzzo 002; Claudio Nani; Costantino Armiento; Alberto L. Sangiovanni-Vincentelli; Jan Craninckx; Geert Van der Plas (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

27.8 A 0.076mm2 12b 26.5mW 600MS/s 4×-interleaved subranging SAR-ΔΣ ADC with on-chip buffer in 28nm CMOS. - Alessandro Venca; Nicola Ghittori; Alessandro Bosi; Claudio Nani (ISSCC, 2016)

A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS. - Alessandro Venca; Nicola Ghittori; Alessandro Bosi; Claudio Nani (IEEE J. Solid State Circuits, 2016)

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET. - Matteo Pisati; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Marco Sosio; Enrico Pozzati; Nicola Ghittori; Federico Magni; Marco Garampazzi; Giacomino Bollati; Antonio Milani; Alberto Minuti; et al. (ISSCC, 2019)

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. - Matteo Pisati; Alberto Minuti; Giacomino Bollati; Fabio Giunco; Roberto G. Massolini; Giovanni Cesura; Fernando De Bernardinis; Paolo Pascale; Claudio Nani; Nicola Ghittori; Enrico Pozzati; Marco Sosio; et al. (IEEE J. Solid State Circuits, 2020)

Delay-lines jitter modeling and efficiency analysis in FinFET technology. - Alessio Di Pasquo; Enrico Monaco; Claudio Nani; Luca Fanucci (ICECS, 2021)

A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC. - Alessio Di Pasquo; Claudio Nani; Enrico Monaco; Luca Fanucci (ISCAS, 2021)

A 0.94 V Dynamic Bias Double Tail Comparator for High-Speed Applications in 5 nm Technology. - Valentina Marazzi; Enrico Monaco; Claudio Nani; Danilo Manstretta (ApplePies, 2023)

Analysis and Design of a Low Power Double Tail Comparator with Dynamic Bias in 5nm FinFET Technology. - Valentina Marazzi; Enrico Monaco; Claudio Nani; Danilo Manstretta (PRIME, 2023)

18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm. - F. Ahmad; A. Mellati; A. Fernandez; A. Iyer; A. Fan; Benjamín T. Reyes; Cindra Abidin; Claudio Nani; D. Albano; Fredy Solis; Gabriele Minoia; Geoff Hatcher; et al. (ISSCC, 2024)

18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET. - R. L. Nguyen; A. Mellati; A. Fernandez; A. Iyer; A. Fan; Benjamín T. Reyes; Cindra Abidin; Claudio Nani; D. Albano; F. Ahmad; Fredy Solis; Gabriele Minoia; et al. (ISSCC, 2024)

A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; D. Albano; C. Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; D. Herbas; et al. (VLSI Technology and Circuits, 2024)

A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (VLSI Technology and Circuits, 2024)

An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process. - Fabio Giunco; Marco Sosio; Claudio Nani; Ivan Fabiano; Travis Lovitt; Victor Karam; Domenico Albano; Claudio Asero; Nicola Codega; Marco Garampazzi; Nicola Ghittori; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)

A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz. - Claudio Nani; Enrico Monaco; Nicola Ghittori; Alessandro Bosi; Domenico Albano; Claudio Asero; Nicola Codega; Alessio Di Pasquo; Ivan Fabiano; Marco Garampazzi; Fabio Giunco; Leonardo Daniel Herbas Burgos; et al. (IEEE J. Solid State Circuits, 2025)