Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis. - Clay Hughes; Tao Li 006 (IISWC, 2008)

TransMetric: architecture independent workload characterization for transactional memory benchmarks. - James Poe; Clay Hughes; Tao Li 006 (ICS, 2009)

On the (dis)similarity of transactional memory workloads. - Clay Hughes; James Poe; Amer Qouneh; Tao Li 006 (IISWC, 2009)

TransPlant: A parameterized methodology for generating transactional memory workloads. - James Poe; Clay Hughes; Tao Li 006 (MASCOTS, 2009)

Optimizing throughput/power trade-offs in hardware transactional memory using DVFS and intelligent scheduling. - Clay Hughes; Tao Li 006 (ICS, 2011)

Real-time hardware design for improving laser detection and ranging accuracy. - Jarrod Brown; Clay Hughes; Linda DeBrunner (ACSCC, 2012)

Performance analysis for using non-volatile memory DIMMs: opportunities and challenges. - Amro Awad; Simon D. Hammond; Clay Hughes; Arun Rodrigues; K. Scott Hemmert; Robert J. Hoekstra (MEMSYS, 2017)

Evaluating the Intel Skylake Xeon Processor for HPC Workloads. - Simon D. Hammond; Courtenay T. Vaughan; Clay Hughes (HPCS, 2018)

Osiris: A Low-Cost Mechanism to Enable Restoration of Secure Non-Volatile Memories. - Mao Ye 008; Clayton Hughes; Amro Awad (MICRO, 2018)

Exploring Allocation Policies in Disaggregated Non-Volatile Memories. - Vamsee Reddy Kommareddy; Amro Awad; Clayton Hughes; Simon David Hammond (MCHPC@SC, 2018)

Evaluating the Marvell ThunderX2 Server Processor for HPC Workloads. - Simon D. Hammond; Clay Hughes; Michael J. Levenhagen; Courtenay T. Vaughan; Andrew J. Younge; Benjamin Schwaller; Michael J. Aguilar; Kevin T. Pedretti; James H. Laros III (HPCS, 2019)

Investigating Fairness in Disaggregated Non-Volatile Memories. - Vamsee Reddy Kommareddy; Clayton Hughes; Simon D. Hammond; Amro Awad (ISVLSI, 2019)

Page migration support for disaggregated non-volatile memories. - Vamsee Reddy Kommareddy; Simon David Hammond; Clayton Hughes; Ahmad Samih; Amro Awad (MEMSYS, 2019)

PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures. - Vamsee Reddy Kommareddy; Jagadish Kotra; Clayton Hughes; Simon David Hammond; Amro Awad (MEMSYS, 2020)

Stealth-Persist: Architectural Support for Persistent Applications in Hybrid Memory Systems. - Mazen Al-Wadi; Vamsee Reddy Kommareddy; Clayton Hughes; Simon David Hammond; Amro Awad (HPCA, 2021)

DeACT: Architecture-Aware Virtual Memory Support for Fabric Attached Memory Systems. - Vamsee Reddy Kommareddy; Clayton Hughes; Simon David Hammond; Amro Awad (HPCA, 2021)

ATHENA: Enabling Codesign for Next-Generation AI/ML Architectures. - Mark Plagge; Ben Feinberg; John McFarland; Fred Rothganger; Sapan Agarwal; Amro Awad; Clayton Hughes; Suma George Cardwell (ICRC, 2022)

Minerva: Rethinking Secure Architectures for the Era of Fabric-Attached Memory Architectures. - Mazen Al-Wadi; Rujia Wang; David Mohaisen; Clayton Hughes; Simon David Hammond; Amro Awad (IPDPS, 2022)

"Smarter" NICs for faster molecular dynamics: a case study. - Sara Karamati; Clayton Hughes; K. Scott Hemmert; Ryan E. Grant; Whit Schonbein; Scott Levy; Thomas M. Conte; Jeffrey Young 001; Richard W. Vuduc (IPDPS, 2022)

FAT-PIM: Low-Cost Error Detection for Processing-In-Memory. - Kazi Abu Zubair; Sumit Kumar Jha 001; David Mohaisen; Clayton Hughes; Amro Awad (CoRR, 2022)

ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit. - Shubham Nema; Shiva Kaushik Chunduru; Charan Kodigal; Gwendolyn Voskuilen; Arun F. Rodrigues; K. Scott Hemmert; Ben Feinberg; Hyokeun Lee; Amro Awad; Clayton Hughes (IISWC, 2023)

Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware. - Luc Berger-Vergiat; Suma George Cardwell; Ben Feinberg; Simon D. Hammond; Clayton Hughes; Michael J. Levenhagen; Kevin T. Pedretti (ISC Workshops, 2023)

SEFsim: A Statistically-Guided Fast DRAM Simulator. - Debpratim Adak; Hyokeun Lee; Ben Feinberg; Gwendolyn Voskuilen; Clayton Hughes; Huiyang Zhou; Amro Awad (ISPASS, 2024)

Integrating RISC-V SIMT and Scalar Cores: Loosely to Tightly Coupled. - Sooraj Chetput; Anusuya Nallathambi; Spencer Bowles; Justin Cambridge; Alex Chitsazzadeh; Gagan Gundala; Zengxiang Han; Johnathan Hong; Guilliame Hu; Ronit Nallagatla; Ansh Patel; Khoi Pham; et al. (ISC Workshops, 2024)

ASLink: Modeling Multi-GPU Execution in Accel-Sim. - Christin Bose; Cesar Avalos; Junrui Pan; Yechen Liu; Mahmoud Khairy; Clay Hughes; Timothy G. Rogers (ISPASS, 2025)