Symbolic functional and timing verification of transistor-level circuits. - Clayton B. McDonald; Randal E. Bryant (ICCAD, 1999)

Symbolic timing simulation using cluster scheduling. - Clayton B. McDonald; Randal E. Bryant (DAC, 2000)

Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis. - Clayton B. McDonald; Randal E. Bryant (DAC, 2001)

A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells. - Clayton B. McDonald; Randal E. Bryant (ICCAD, 2001)

CMOS circuit verification with symbolic switch-level timingsimulation. - Clayton B. McDonald; Randal E. Bryant (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States. - Clayton B. McDonald; Hsinwei Chou; Vijay Durairaj; Pey-Chang Kent Lin (ICCAD, 2015)