On improved graph-based alternative wiring scheme for multi-level logic optimization. - Yu-Liang Wu; Chin Ngai Sze; Chak-Chung Cheung; Hongbing Fan (ICECS, 2000)

Improved alternative wiring scheme applying dominator relationship. - Chin Ngai Sze; Yu-Liang Wu (ASP-DAC, 2001)

Optimal circuit clustering with variable interconnect delay. - Cliff C. N. Sze; Ting-Chi Wang (ISCAS (4), 2002)

Multi-Level Circuit Clustering for Delay Minimization. - Cliff C. N. Sze; Ting-Chi Wang (IWLS, 2002)

Accelerating Logic Rewiring Using Implication Analysis Tree. - Chin Ngai Sze; Wangning Long; Yu-Liang Wu; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Performance-driven multi-level clustering for combinational circuits. - Chin Ngai Sze; Ting-Chi Wang (ASP-DAC, 2003)

Optimal circuit clustering for delay minimization under a more general delay model. - Cliff C. N. Sze; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

A place and route aware buffered Steiner tree construction. - Cliff C. N. Sze; Jiang Hu; Charles J. Alpert (ASP-DAC, 2004)

Porosity-aware buffered Steiner tree construction. - Charles J. Alpert; Gopal Gandham; Milos Hrkic; Jiang Hu; Stephen T. Quay; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Multilevel circuit clustering for delay minimization. - Cliff C. N. Sze; Ting-Chi Wang; Li-C. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Making fast buffer insertion even faster via approximation techniques. - Zhuo Li 001; Cliff C. N. Sze; Charles J. Alpert; Jiang Hu; Weiping Shi (ASP-DAC, 2005)

Register placement for low power clock network. - Yongqiang Lu 001; Cliff C. N. Sze; Xianlong Hong; Qiang Zhou 001; Yici Cai; Liang Huang; Jiang Hu (ASP-DAC, 2005)

Skew scheduling and clock routing for improved tolerance to process variations. - Ganesh Venkataraman; Cliff C. N. Sze; Jiang Hu (ASP-DAC, 2005)

Navigating registers in placement for clock network minimization. - Yongqiang Lu 001; Cliff C. N. Sze; Xianlong Hong; Qiang Zhou 001; Yici Cai; Liang Huang; Jiang Hu (DAC, 2005)

Navigating Register Placement for Low Power Clock Network Design. - Yongqiang Lu 001; Chin Ngai Sze; Xianlong Hong; Qiang Zhou 001; Yici Cai; Liang Huang; Jiang Hu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Timing-driven Steiner trees are (practically) free. - Charles J. Alpert; Andrew B. Kahng; Cliff C. N. Sze; Qinke Wang (DAC, 2006)

Integrated placement and skew optimization for rotary clocking. - Ganesh Venkataraman; Jiang Hu; Frank Liu 001; Cliff C. N. Sze (DATE, 2006)

Accurate estimation of global buffer delay within a floorplan. - Charles J. Alpert; Jiang Hu; Sachin S. Sapatnekar; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

The nuts and bolts of physical synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (SLIP, 2007)

Techniques for Fast Physical Synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (Proc. IEEE, 2007)

Fast Algorithms for Slew-Constrained Minimum Cost Buffering. - Shiyan Hu 001; Charles J. Alpert; Jiang Hu; Shrirang K. Karandikar; Zhuo Li 001; Weiping Shi; Chin Ngai Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Path-Based Buffer Insertion. - Chin Ngai Sze; Charles J. Alpert; Jiang Hu; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Algorithms for the scaling toward nanometer VLSI physical synthesis. - Chin Ngai Sze (2007)

Pyramids: an efficient computational geometry-based approach for timing-driven placement. - Tao Luo 002; David A. Papa; Zhuo Li 001; Chin Ngai Sze; Charles J. Alpert; David Z. Pan (ICCAD, 2008)

The ISPD global routing benchmark suite. - Gi-Joon Nam; Cliff C. N. Sze; Mehmet Can Yildiz (ISPD, 2008)

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. - David A. Papa; Tao Luo 002; Michael D. Moffitt; Chin Ngai Sze; Zhuo Li 001; Gi-Joon Nam; Charles J. Alpert; Igor L. Markov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Timing-Driven Interconnect Synthesis. - Jiang Hu; Gabriel Robins; Cliff C. N. Sze (Handbook of Algorithms for Physical Design Automation, 2008)

Buffering in the Layout Environment. - Jiang Hu; Cliff C. N. Sze (Handbook of Algorithms for Physical Design Automation, 2008)

Ispd2009 clock network synthesis contest. - Cliff N. Sze; Phillip J. Restle; Gi-Joon Nam; Charles J. Alpert (ISPD, 2009)

A methodology for propagating design tolerances to shape tolerances for use in manufacturing. - Shayak Banerjee; Kanak B. Agarwal; Chin Ngai Sze; Sani R. Nassif; Michael Orshansky (DATE, 2010)

Ultra-fast interconnect driven cell cloning for minimizing critical path delay. - Zhuo Li 001; David A. Papa; Charles J. Alpert; Shiyan Hu 001; Weiping Shi; Cliff C. N. Sze; Nancy Ying Zhou (ISPD, 2010)

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results. - Cliff C. N. Sze (ISPD, 2010)

Wire synthesizable global routing for timing closure. - Michael D. Moffitt; Chin Ngai Sze (ASP-DAC, 2011)

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. - Feifei Niu; Qiang Zhou 001; Hailong Yao; Yici Cai; Jianlei Yang 001; Chin Ngai Sze (ACM Great Lakes Symposium on VLSI, 2011)

The future of clock network synthesis. - Cliff C. N. Sze (ICCAD, 2011)

Grid-to-ports clock routing for high performance microprocessor designs. - Haitong Tian; Wai-Chung Tang; Evangeline F. Y. Young; Cliff C. N. Sze (ISPD, 2011)

The ISPD-2011 routability-driven placement contest and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Gi-Joon Nam; Jarrod A. Roy (ISPD, 2011)

Quantifying academic placer performance on custom designs. - Samuel I. Ward; David A. Papa; Zhuo Li 001; Cliff N. Sze; Charles J. Alpert; Earl E. Swartzlander Jr. (ISPD, 2011)

Design methodology for the IBM POWER7 microprocessor. - Joshua Friedrich; Ruchir Puri; Uwe Brandt; Markus Bühler; Jack DiLullo; Jeremy Hopkins; Mozammel Hossain; Michael A. Kazda; Joachim Keinert; Zahi M. Kurzum; Douglass Lamb; Alice Lee; et al. (IBM J. Res. Dev., 2011)

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. - David A. Papa; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Natarajan Viswanathan; Gi-Joon Nam; Igor L. Markov (IEEE Micro, 2011)

Shedding Physical Synthesis Area Bloat. - Nancy Ying Zhou; Charles J. Alpert; Zhuo Li 001; Cliff N. Sze; Louise Trevillyan (VLSI Design, 2011)

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. - Zhuo Li 001; Charles J. Alpert; Gi-Joon Nam; Cliff C. N. Sze; Natarajan Viswanathan; Nancy Y. Zhou (DAC, 2012)

The DAC 2012 routability-driven placement contest and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Yaoguang Wei (DAC, 2012)

GLARE: global and local wiring aware routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (DAC, 2012)

WRIP: logic restructuring techniques for wirelength-driven incremental placement. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ACM Great Lakes Symposium on VLSI, 2012)

Placement: Hot or Not? - Charles J. Alpert; Zhuo Li 001; Gi-Joon Nam; Chin Ngai Sze; Natarajan Viswanathan; Samuel I. Ward (ICCAD, 2012)

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Yaoguang Wei (ICCAD, 2012)

Postgrid Clock Routing for High Performance Microprocessor Designs. - Haitong Tian; Wai-Chung Tang; Evangeline F. Y. Young; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ASP-DAC, 2013)

Routing congestion estimation with real design constraints. - Wen-Hao Liu 001; Yaoguang Wei; Cliff C. N. Sze; Charles J. Alpert; Zhuo Li 001; Yih-Lang Li; Natarajan Viswanathan (DAC, 2013)

CATALYST: planning layer directives for effective design closure. - Yaoguang Wei; Zhuo Li 001; Cliff C. N. Sze; Shiyan Hu 001; Charles J. Alpert; Sachin S. Sapatnekar (DATE, 2013)

Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo. - Thomas H. Osiecki; Min-Yu Tsai; Anne E. Gattiker; Damir A. Jamsek; Sani R. Nassif; William Evan Speight; Cliff C. N. Sze (ICCS, 2013)

Clock power minimization using structured latch templates and decision tree induction. - Samuel I. Ward; Natarajan Viswanathan; Nancy Y. Zhou; Cliff C. N. Sze; Zhuo Li 001; Charles J. Alpert; David Z. Pan (ICCAD, 2013)

ISPD 2013 expert designer/user session (eds). - Cliff C. N. Sze; Laleh Behjat; Nikhil Jayakumar; Atul Walimbe; Gregory Ford; Mark Zwolinski; Harish Dangat; Giriraj Kakol (ISPD, 2013)

Pacman: driving nonuniform clock grid loads for low-skew robust clock network. - Nancy Y. Zhou; Phillip J. Restle; Joseph N. Palumbo; Joseph N. Kozhaya; Haifeng Qian; Zhuo Li 001; Charles J. Alpert; Cliff C. N. Sze (SLIP, 2014)

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. - Cheng-Kok Koh; Chin Ngai Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Techniques for scalable and effective routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2014)

Gate sizing and threshold voltage assignment for high performance microprocessor designs. - Tiago Reimann; Cliff C. N. Sze; Ricardo Reis 001 (ASP-DAC, 2015)

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. - Azadeh Davoodi; Jiang Hu; Muhammet Mustafa Ozdal; Cliff C. N. Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. - Yici Cai; Chao Deng; Qiang Zhou 001; Hailong Yao; Feifei Niu; Cliff N. Sze (IEEE Trans. Very Large Scale Integr. Syst., 2015)

GPU acceleration for Bayesian control of Markovian genetic regulatory networks. - He Zhou; Jiang Hu; Sunil P. Khatri; Frank Liu 001; Cliff C. N. Sze; Mohammadmahdi R. Yousefi (BHI, 2016)

Cell Selection for High-Performance Designs in an Industrial Design Flow. - Tiago J. Reimann; Cliff C. N. Sze; Ricardo Reis 001 (ISPD, 2016)

Challenges of cell selection algorithms in industrial high performance microprocessor designs. - Tiago Reimann; Cliff C. N. Sze; Ricardo Reis 001 (Integr., 2016)

Fast and Highly Scalable Bayesian MDP on a GPU Platform. - He Zhou; Sunil P. Khatri; Jiang Hu; Frank Liu 001; Cliff C. N. Sze (BCB, 2017)

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration. - Johann Knechtel; Ozgur Sinanoglu; Ibrahim Abe M. Elfadel; Jens Lienig; Cliff C. N. Sze (IPSJ Trans. Syst. LSI Des. Methodol., 2017)