Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. - Johann Glaser; Clifford Wolf (FDL (Selected Papers), 2012)

Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic. - Clifford Wolf; Johann Glaser; Florian Schupfer; Jan Haase 001; Christoph Grimm 001 (FDL, 2012)

Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow. - Christian Krieg; Clifford Wolf; Axel Jantsch (ICCAD, 2016)

Toggle MUX: How X-Optimism Can Lead to Malicious Hardware. - Christian Krieg; Clifford Wolf; Axel Jantsch; Tanja Zseby (DAC, 2017)

Btor2 , BtorMC and Boolector 3.0. - Aina Niemetz; Mathias Preiner; Clifford Wolf; Armin Biere (CAV (1), 2018)

Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. - David Shah; Eddie Hung; Clifford Wolf; Serge Bazanski; Dan Gisselquist; Miodrag Milanovic (FCCM, 2019)