Automatic post-layout flow validation tool for Deep Sub-micron process design kits. - Pinping Sun; Cole Zemke; Wayne H. Woods; Nick Perez; Hailing Wang; Essam Mina; Barbara Dewitt (ISQED, 2011)

Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology. - Motoi Ichihashi; Jia Zeng; Cole Zemke; Irene Lin; Greg Northrop; Ning Jin; Jongwook Kye (SoCC, 2016)