Colin Schmidt

Orcid: 0000-0001-9958-6045

Affiliations:
  • University of California, Berkeley, CA, USA


According to our database1, Colin Schmidt authored at least 16 papers between 2016 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.
IEEE J. Solid State Circuits, 2022

Hammer: a modular and reusable physical design flow tool: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 16mm<sup>2</sup> 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET.
Proceedings of the 47th ESSCIRC 2021, 2021

An Automated and Process-Portable Generator for Phase-Locked Loop.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

A Methodology for Reusable Physical Design.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.
IEEE Micro, 2019

Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures.
CoRR, 2019

2017
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017

Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Vector Processors for Energy-Efficient Embedded Systems.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016


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