A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. - Colin Weltin-Wu; Enrico Temporiti; Daniele Baldi; Francesco Svelto (ISSCC, 2008)

Insights into wideband fractional All-Digital PLLs for RF applications. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Riccardo Tonietto; Francesco Svelto (CICC, 2009)

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Riccardo Tonietto; Francesco Svelto (IEEE J. Solid State Circuits, 2009)

A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. - Colin Weltin-Wu; Enrico Temporiti; Daniele Baldi; Marco Cusmai; Francesco Svelto (ISSCC, 2010)

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. - Enrico Temporiti; Colin Weltin-Wu; Daniele Baldi; Marco Cusmai; Francesco Svelto (IEEE J. Solid State Circuits, 2010)

Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. - Colin Weltin-Wu; Enrico Temporiti; Marco Cusmai; Daniele Baldi; Francesco Svelto (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity. - Mariya Kurchuk; Colin Weltin-Wu; Dominique Morche; Yannis P. Tsividis (ISSCC, 2011)

An event-driven, alias-free ADC with signal-dependent resolution. - Colin Weltin-Wu; Yannis P. Tsividis (VLSIC, 2012)

Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation. - Mariya Kurchuk; Colin Weltin-Wu; Dominique Morche; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2012)

An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution. - Colin Weltin-Wu; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2013)

25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. - Colin Weltin-Wu; Guobi Zhao; Ian Galton (ISSCC, 2015)

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. - Colin Weltin-Wu; Guobi Zhao; Ian Galton (IEEE J. Solid State Circuits, 2015)

A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. - Colin Weltin-Wu; Eythan Familier; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement. - Ian Galton; Colin Weltin-Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. - Enrique Alvarez-Fontecilla; Amr I. Eissa; Eslam Helal; Colin Weltin-Wu; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs. - Amr I. Eissa; Enrique Alvarez-Fontecilla; Colin Weltin-Wu; Ian Galton (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)