A Network Based Functional Verification Method of IEEE 1394a PHY Core. - Colin Yu Lin; Song Cao; Junshe An; Fei Han; Qifei Fan (ISVLSI, 2008)

Operation scheduling for FPGA-based reconfigurable computers. - Colin Yu Lin; Ngai Wong 001; Hayden Kwok-Hay So (FPL, 2009)

Design space exploration for sparse matrix-matrix multiplication on FPGAs. - Colin Yu Lin; Zheng Zhang 005; Ngai Wong 001; Hayden Kwok-Hay So (FPT, 2010)

A Model for Peak Matrix Performance on FPGAs. - Colin Yu Lin; Hayden Kwok-Hay So; Philip Heng Wai Leong (FCCM, 2011)

A Model for Matrix Multiplication Performance on FPGAs. - Colin Yu Lin; Hayden Kwok-Hay So; Philip Heng Wai Leong (FPL, 2011)

Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only). - Colin Yu Lin; Ngai Wong 001; Hayden Kwok-Hay So (FPGA, 2012)

Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis. - Colin Yu Lin; Hayden Kwok-Hay So (SIGARCH Comput. Archit. News, 2012)

A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency. - Cheng Liu 008; Colin Yu Lin; Hayden Kwok-Hay So (FCCM, 2013)

Timing-constrained minimum area/power FPGA memory mapping. - Fangqing Du; Colin Yu Lin; Xiuhai Cui; Jiabin Sun; Feng Liu; Fei Liu 011; Haigang Yang (FPL, 2013)

Design space exploration for sparse matrix-matrix multiplication on FPGAs. - Colin Yu Lin; Ngai Wong 001; Hayden Kwok-Hay So (Int. J. Circuit Theory Appl., 2013)

A survey of open source processors for FPGAs. - Rui Jia; Colin Yu Lin; Zhenhong Guo; Rui Chen 014; Fei Wang; Tongqiang Gao; Haigang Yang (FPL, 2014)

Exploring architecture parameters for dual-output LUT based FPGAs. - Zhenghong Jiang; Colin Yu Lin; Liqun Yang; Fei Wang; Haigang Yang (FPL, 2014)

A semi-supervised modeling approach for performance characterization of FPGA architectures. - Liqun Yang; Haigang Yang; Wei Li 008; Zhihua Li; Zhihong Huang; Colin Yu Lin (FPL, 2014)

Size aware placement for island style FPGAs. - Junying Huang; Colin Yu Lin; Yang Liu; Zhihua Li; Haigang Yang (FPT, 2014)

A technology mapper for depth-constrained FPGA logic cells. - Zhenghong Jiang; Grace Zgheib; Colin Yu Lin; David Novo; Zhihong Huang; Liqun Yang; Haigang Yang; Paolo Ienne (FPL, 2015)

FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. - Colin Yu Lin; Zhenghong Jiang; Cheng Fu; Hayden Kwok-Hay So; Haigang Yang (SIGARCH Comput. Archit. News, 2016)

A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability. - Rui Jia; Hai-Gang Yang; Colin Yu Lin; Rui Chen 014; Xin-Gang Wang; Zhenhong Guo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform. - Weiyun Jiang; Kaiqi Zhang 002; Colin Yu Lin; Feng Xing; Zheng Zhang 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)