Using a Performance Model to Implement a Superscalar CVA6. - Côme Allart; Jean-Roch Coulon; André Sintzoff; Olivier Potin; Jean-Baptiste Rigaud (CF (Companion), 2024)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)