A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder. - Cong Liu 014; Weiwei Shen; Tianlong Ma; Yibo Fan; Xiaoyang Zeng (ASICON, 2013)

A fast 8×8 IDCT algorithm for HEVC. - Tianlong Ma; Cong Liu 014; Yibo Fan; Xiaoyang Zeng (ASICON, 2013)

A Combined Deblocking Filter and SAO Hardware Architecture for HEVC. - Weiwei Shen; Yibo Fan; Yufeng Bai; Leilei Huang; Qing Shang; Cong Liu 014; Xiaoyang Zeng (IEEE Trans. Multim., 2016)