A novel architecture of local memory for programmable SIMD vision chip. - Zhe Chen; Jie Yang 033; Cong Shi 003; Nanjian Wu (ASICON, 2013)

7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. - Cong Shi 003; Jie Yang 033; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nanjian Wu; Zhihua Wang 001 (ISSCC, 2014)

A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip. - Cong Shi 003; Jie Yang 033; Liyuan Liu; Nanjian Wu; ZhiHua Wang 001 (Sci. China Inf. Sci., 2014)

A high speed multi-level-parallel array processor for vision chips. - Cong Shi 003; Jie Yang 033; Nanjian Wu; ZhiHua Wang 001 (Sci. China Inf. Sci., 2014)

A high speed 1000 fps CMOS image sensor with low noise global shutter pixels. - Yangfan Zhou; Zhongxiang Cao; Qi Qin; Quanliang Li; Cong Shi 003; Nanjian Wu (Sci. China Inf. Sci., 2014)

A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. - Cong Shi 003; Jie Yang 033; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nanjian Wu; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2014)

A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor. - Yangfan Zhou; Zhongxiang Cao; Ye Han; Quanliang Li; Cong Shi 003; Runjiang Dou; Qi Qin; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2015)

Exploiting Lightweight Statistical Learning for Event-Based Vision Processing. - Cong Shi 003; Jiajun Li; Ying Wang 001; Gang Luo 003 (IEEE Access, 2018)

A Streaming Motion Magnification Core for Smart Image Sensors. - Cong Shi 003; Gang Luo 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Compact VLSI System for Bio-Inspired Visual Motion Estimation. - Cong Shi 003; Gang Luo 003 (IEEE Trans. Circuits Syst. Video Technol., 2018)

20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. - Junxian He; Xichuan Zhou; Yingcheng Lin; Chonglei Sun; Cong Shi 003; Nanjian Wu; Gang Luo 003 (ASICON, 2019)

High-speed Classification of AER Data Based on a Low-cost Hardware System. - Jinguo Huang; Yingcheng Lin; Wei He; Xichuan Zhou; Cong Shi 003; Nanjian Wu; Gang Luo 003 (ASICON, 2019)

Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Video Analysis. - Yongchen Wang; Ying Wang 001; Huawei Li 001; Cong Shi 003; Xiaowei Li 001 (DAC, 2019)

A Hardware-Friendly Optical Flow-Based Time-to-Collision Estimation Algorithm. - Cong Shi 003; Zhuoran Dong; Shrinivas J. Pundlik; Gang Luo 003 (Sensors, 2019)

BitPruner: Network Pruning for Bit-serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (DAC, 2020)

MoNet3D: Towards Accurate Monocular 3D Object Localization in Real Time. - Xichuan Zhou; Yicong Peng; Chunqiao Long; Fengbo Ren; Cong Shi 003 (ICML, 2020)

A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution. - Yingcheng Lin; Rui Li; Wei He; Xichuan Zhou; Junxian He; Ping Li 042; Ying Jiang; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2020)

Neural Network Activation Quantization with Bitwise Information Bottlenecks. - Xichuan Zhou; Kui Liu; Cong Shi 003; Haijun Liu 001; Ji Liu (CoRR, 2020)

A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. - Wei He; Jinguo Huang; Tengxiao Wang; Yingcheng Lin; Junxian He; Xichuan Zhou; Ping Li 042; Ying Wang 001; Nanjian Wu; Cong Shi 003 (Sensors, 2020)

Optimizing Information Theory Based Bitwise Bottlenecks for Efficient Mixed-Precision Activation Quantization. - Xichuan Zhou; Kui Liu; Cong Shi 003; Haijun Liu 001; Ji Liu (AAAI, 2021)

Exploiting Memristors for Neuromorphic Reinforcement Learning. - Cong Shi 003; Jing Lu; Ying Wang 001; Ping Li 042; Min Tian (AICAS, 2021)

A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors. - Yingcheng Lin; Rui Li; Wei He; Xichuan Zhou; Junxian He; Ping Li 042; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2021)

TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning. - Haibing Wang; Zhen He; Jinsong Rao; Tengxiao Wang; Junxian He; Min Tian; Xichuan Zhou; Liyuan Liu; Nanjian Wu; Cong Shi 003 (ICTA, 2021)

A Heterogeneous Spiking Neural Network for Computationally Efficient Face Recognition. - Xichuan Zhou; Zhenghua Zhou; Zhengqing Zhong; Jianyi Yu; Tengxiao Wang; Min Tian; Ying Jiang; Cong Shi 003 (ISCAS, 2021)

CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. - Tengxiao Wang; Cong Shi 003; Xichuan Zhou; Yingcheng Lin; Junxian He; Ping Gan; Ping Li 042; Ying Wang 001; Liyuan Liu; Nanjian Wu; Gang Luo 003 (Neurocomputing, 2021)

Hapke Data Augmentation for Deep Learning-Based Hyperspectral Data Analysis With Limited Samples. - Kai Qin; Fangyuan Ge; Yingjun Zhao; Ling Zhu; Ming Li; Cong Shi 003; Dong Li 007; Xichuan Zhou (IEEE Geosci. Remote. Sens. Lett., 2021)

A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. - Ling Zhang; Jing Yang 067; Cong Shi 003; Yingcheng Lin; Wei He; Xichuan Zhou; Xu Yang 004; Liyuan Liu; Nanjian Wu (Sensors, 2021)

An Edge 3D CNN Accelerator for Low-Power Activity Recognition. - Ying Wang 001; Yongchen Wang; Cong Shi 003; Long Cheng 003; Huawei Li 001; Xiaowei Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features. - Wei He; Jie Zhang; Yingcheng Lin; Xichuan Zhou; Ping Li 042; Liyuan Liu; Nanjian Wu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks. - Cong Shi 003; Tengxiao Wang; Junxian He; Jianghao Zhang; Liyuan Liu; Nanjian Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks. - Tengxiao Wang; Haibing Wang; Junxian He; Zhengqing Zhong; Fang Tang; Xichuan Zhou; Shuangming Yu; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (BioCAS, 2022)

A Lightweight Spiking GAN Model for Memristor-centric Silicon Circuit with On-chip Reinforcement Adversarial Learning. - Min Tian; Jing Lu; Haoran Gao; Haibing Wang; Jianyi Yu; Cong Shi 003 (ISCAS, 2022)

TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity. - Haibing Wang; Zhen He; Tengxiao Wang; Junxian He; Xichuan Zhou; Ying Wang 001; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (IEEE Trans. Biomed. Circuits Syst., 2022)

A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. - Zhen He; Cong Shi 003; Tengxiao Wang; Ying Wang 001; Min Tian; Xichuan Zhou; Ping Li 042; Liyuan Liu; Nanjian Wu; Gang Luo 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip. - Zhengqing Zhong; Tengxiao Wang; Haibing Wang; Zhihua Zhou; Junxian He; Fang Tang; Xichuan Zhou; Shuangming Yu; Liyuan Liu; Nanjian Wu; Min Tian; Cong Shi 003 (AICAS, 2023)

MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning. - Tengxiao Wang; Min Tian; Zhengqing Zhong; Haibing Wang; Junxian He; Fang Tang; Xichuan Zhou; Shuangming Yu; Nanjian Wu; Liyuan Liu; Cong Shi 003 (A-SSCC, 2023)

A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors. - Fuming Lei; Xu Yang 017; Jian Liu 021; Nanjian Wu; Cong Shi 003; Runjiang Dou; Liyuan Liu (ICTA, 2023)

Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests. - Cong Shi 003; Junxian He; Shrinivas J. Pundlik; Xichuan Zhou; Nanjian Wu; Gang Luo 003 (Sci. China Inf. Sci., 2023)

Network Pruning for Bit-Serial Accelerators. - Xiandong Zhao; Ying Wang 001; Cheng Liu 008; Cong Shi 003; Kaijie Tu; Lei Zhang 008 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

An Edge Neuromorphic Hardware With Fast On-Chip Error-Triggered Learning on Compressive Sensed Spikes. - Cong Shi 003; Jingya Zhang; Tengxiao Wang; Zhengqing Zhong; Junxian He; Haoran Gao; Jianyi Yu; Ping Li 042; Min Tian (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. - Leyi Chen; Cong Shi 003; Junxian He; Jianyi Yu; Haibing Wang; Jing Lu; Liyuan Liu; Nanjian Wu; Min Tian (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods. - Lei Kang; Xu Yang 017; Chi Zhang; Shuangming Yu; Runjiang Dou; Wenchang Li; Cong Shi 003; Jian Liu 021; Nanjian Wu; Liyuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Learnable Leakage and Onset-Spiking Self-Attention in SNNs with Local Error Signals. - Cong Shi 003; Li Wang; Haoran Gao; Min Tian (Sensors, 2023)

A visual cortex-inspired edge neuromorphic hardware architecture with on-chip multi-layer STDP learning. - Junxian He; Min Tian; Ying Jiang; Haibing Wang; Tengxiao Wang; Xichuan Zhou; Liyuan Liu; Nanjian Wu; Ying Wang 001; Cong Shi 003 (Comput. Electr. Eng., 2024)

STOP: Spatiotemporal Orthogonal Propagation for Weight-Threshold-Leakage Synergistic Training of Deep Spiking Neural Networks. - Haoran Gao; Xichuan Zhou; Yingcheng Lin; Min Tian; Liyuan Liu; Cong Shi 003 (CoRR, 2024)

LLD-GAN: An end-to-end network for low-light image demosaicking. - Li Wang; Cong Shi 003; Shrinivas J. Pundlik; Xu Yang; Liyuan Liu; Gang Luo 003 (Displays, 2024)

A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips. - Siyuan Wei; Ke Ning; Lei Kang; Xuemin Zheng; Mingxin Zhao; Mengmeng Xu; Shuyu Wang; Xuanzhe Xu; Runjiang Dou; Shuangming Yu; Xu Yang 017; Jian Liu 021; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning. - Cong Shi 003; Xiang Fu; Haibing Wang; Yingcheng Lin; Ying Jiang; Liyuan Liu; Nanjian Wu; Min Tian (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference. - Zhengqing Zhong; Haibing Wang; Mingju Chen; Yingcheng Lin; Min Tian; Tengxiao Wang; Liyuan Liu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

MorphBungee: A 65-nm 7.2-mm2 27-µJ/Image Digital Edge Neuromorphic Chip With on-Chip 802-Frame/s Multi-Layer Spiking Neural Network Learning. - Tengxiao Wang; Min Tian; Haibing Wang; Zhengqing Zhong; Junxian He; Fang Tang; Xichuan Zhou; Yingcheng Lin; Shuangming Yu; Liyuan Liu; Cong Shi 003 (IEEE Trans. Biomed. Circuits Syst., 2025)

An Edge Neuromorphic Processor With High-Accuracy On-Chip Aggregate-Label Learning. - Guanyu Chen; Mingju Chen; Tengxiao Wang; Haibing Wang; Xiang Fu; Yingcheng Lin; Liyuan Liu; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Visual-Cortex-Mimetic Tiny Neuromorphic Vision Processor Based on Reconfigurable Cortical Neuron Unit. - Mingju Chen; Junxian He; Haibing Wang; Tengxiao Wang; Haoran Gao; Liyuan Liu; Ying Wang 001; Cong Shi 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)