Impact of process variations on emerging memristor. - Dimin Niu; Yiran Chen 001; Cong Xu 002; Yuan Xie 001 (DAC, 2010)

Design implications of memristor-based RRAM cross-point structures. - Cong Xu 002; Xiangyu Dong 001; Norman P. Jouppi; Yuan Xie 001 (DATE, 2011)

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. - Cong Xu 002; Dimin Niu; Xiaochun Zhu; Seung-Hyuk Kang; Matt Nowak; Yuan Xie 001 (ICCAD, 2011)

Bandwidth-aware reconfigurable cache design with hybrid memory technologies. - Jishen Zhao; Cong Xu 002; Yuan Xie 001 (ICCAD, 2011)

Moguls: a model to explore the memory hierarchy for bandwidth improvements. - Guangyu Sun 003; Christopher J. Hughes; Changkyu Kim; Jishen Zhao; Cong Xu 002; Yuan Xie 001; Yen-Kuang Chen (ISCA, 2011)

When to forget: A system-level perspective on STT-RAMs. - Karthik Swaminathan; Raghav Pisolkar; Cong Xu 002; Vijaykrishnan Narayanan (ASP-DAC, 2012)

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. - Adwait Jog; Asit K. Mishra; Cong Xu 002; Yuan Xie 001; Vijaykrishnan Narayanan; Ravishankar R. Iyer 001; Chita R. Das (DAC, 2012)

Modeling and design exploration of FBDRAM as on-chip memory. - Guangyu Sun 003; Cong Xu 002; Yuan Xie 001 (DATE, 2012)

Design trade-offs for high density cross-point resistive memory. - Dimin Niu; Cong Xu 002; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (ISLPED, 2012)

NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. - Xiangyu Dong 001; Cong Xu 002; Yuan Xie 001; Norman P. Jouppi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Understanding the trade-offs in multi-level cell ReRAM memory design. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (DAC, 2013)

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. - Dimin Niu; Cong Xu 002; Naveen Muralimanohar; Norman P. Jouppi; Yuan Xie 001 (ICCAD, 2013)

Low power multi-level-cell resistive memory design with incomplete data mapping. - Dimin Niu; Qiaosha Zou; Cong Xu 002; Yuan Xie 001 (ICCD, 2013)

Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system. - Tao Zhang 032; Cong Xu 002; Yuan Xie 001; Guangyu Sun 003 (ICCD, 2013)

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. - Cong Xu 002; Dimin Niu; Shimeng Yu; Yuan Xie 001 (ASP-DAC, 2014)

Reliability-aware cross-point resistive memory design. - Cong Xu 002; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2014)

3D-SWIFT: a high-performance 3D-stacked wide IO DRAM. - Tao Zhang 032; Cong Xu 002; Ke Chen 020; Guangyu Sun 003; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2014)

TSV power supply array electromigration lifetime analysis in 3D ICS. - Qiaosha Zou; Tao Zhang 032; Cong Xu 002; Yuan Xie 001 (ACM Great Lakes Symposium on VLSI, 2014)

Adaptive placement and migration policy for an STT-RAM-based hybrid cache. - Zhe Wang 023; Daniel A. Jiménez; Cong Xu 002; Guangyu Sun 003; Yuan Xie 001 (HPCA, 2014)

CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture. - Tao Zhang 032; Matthew Poremba; Cong Xu 002; Guangyu Sun 003; Yuan Xie 001 (HPCA, 2014)

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. - Ping Chi; Cong Xu 002; Tao Zhang 032; Xiangyu Dong 001; Yuan Xie 001 (ICCAD, 2014)

Architecting 3D vertical resistive memory for next-generation storage systems. - Cong Xu 002; Pai-Yu Chen; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ICCAD, 2014)

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation. - Tao Zhang 032; Ke Chen 020; Cong Xu 002; Guangyu Sun 003; Tao Wang 004; Yuan Xie 001 (ISCA, 2014)

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. - Ping Chi; Cong Xu 002; Xiaochun Zhu; Yuan Xie 001 (ISQED, 2014)

Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues. - Yang Zheng; Cong Xu 002; Yuan Xie 001 (ASP-DAC, 2015)

Overcoming the challenges of crossbar resistive memory architectures. - Cong Xu 002; Dimin Niu; Naveen Muralimanohar; Rajeev Balasubramonian; Tao Zhang 032; Shimeng Yu; Yuan Xie 001 (HPCA, 2015)

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. - Ke Chen 020; Sheng Li 007; Jung Ho Ahn; Naveen Muralimanohar; Jishen Zhao; Cong Xu 002; Seongil O; Yuan Xie 001; Jay B. Brockman; Norman P. Jouppi (ICS, 2015)

Memory and Storage System Design with Nonvolatile Memory Technologies. - Jishen Zhao; Cong Xu 002; Ping Chi; Yuan Xie 001 (Inf. Media Technol., 2015)

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. - Cong Xu 002; Yang Zheng; Dimin Niu; Xiaochun Zhu; Seung-Hyuk Kang; Yuan Xie 001 (IEEE Trans. Multi Scale Comput. Syst., 2015)

Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. - Cong Xu 002; Dimin Niu; Yang Zheng; Shimeng Yu; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation. - Enes Eken; Linghao Song; Ismail Bayram; Cong Xu 002; Wujie Wen; Yuan Xie 001; Yiran Chen 001 (DAC, 2016)

Pinatubo: a processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories. - Shuangchen Li; Cong Xu 002; Qiaosha Zou; Jishen Zhao; Yu Lu; Yuan Xie 001 (DAC, 2016)

NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. - Shuangchen Li; Liu Liu 017; Peng Gu; Cong Xu 002; Yuan Xie 001 (ICCAD, 2016)

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. - Ping Chi; Shuangchen Li; Cong Xu 002; Tao Zhang 032; Jishen Zhao; Yongpan Liu; Yu Wang 002; Yuan Xie 001 (ISCA, 2016)

BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories. - Jishen Zhao; Cong Xu 002; Tao Zhang 032; Yuan Xie 001 (J. Comput. Sci. Technol., 2016)

Coordinating Filters for Faster Deep Neural Networks. - Wei Wen; Cong Xu 002; Chunpeng Wu; Yandan Wang; Yiran Chen 001; Hai Li 001 (ICCV, 2017)

TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning. - Wei Wen; Cong Xu 002; Feng Yan 001; Chunpeng Wu; Yandan Wang; Yiran Chen 001; Hai Li 001 (NIPS, 2017)

Toward Cost-Effective Memory Scaling in Clouds: Symbiosis of Virtual and Physical Memory. - Xinying Wang 001; Cong Xu 002; Ke Wang 012; Feng Yan 001; Dongfang Zhao 001 (IEEE CLOUD, 2018)

SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning. - Wei Wen; Yandan Wang; Feng Yan 001; Cong Xu 002; Yiran Chen 001; Hai Li 001 (CoRR, 2018)

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. - Shouyi Yin; Shibin Tang; Xinhan Lin; Peng Ouyang; Fengbin Tu; Leibo Liu; Jishen Zhao; Cong Xu 002; Shuangchen Li; Yuan Xie 001; Shaojun Wei (IEEE Trans. Parallel Distributed Syst., 2019)

Memory Scaling of Cloud-Based Big Data Systems: A Hybrid Approach. - Xinying Wang 001; Cong Xu 002; Ke Wang 012; Feng Yan 001; Dongfang Zhao 001 (IEEE Trans. Big Data, 2022)