Flexible cation-based threshold selector for resistive switching memory integration. - Xiaolong Zhao; Rui Wang; Xiangheng Xiao; Congyan Lu; Facai Wu; Rongrong Cao; Changzhong Jiang; Qi Liu 010 (Sci. China Inf. Sci., 2018)

A physical model for dual gate a-InGaZnO thin film transistors based on multiple trapping and release mechanism. - Linan Li; Wenqiang Ba; Wei Wang 209; Ling Li 013; Guangwei Xu; Lingfei Wang; Zhuoyu Ji; Congyan Lu; Writam Banerjee (Microelectron. J., 2019)

Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec. - Kaifei Chen; Jiebin Niu; Guanhua Yang; Menggan Liu; Wendong Lu; Fuxi Liao; Kailiang Huang; Xinlv Duan; Congyan Lu; Jiawei Wang; Lingfei Wang; Mengmeng Li; et al. (VLSI Technology and Circuits, 2022)

Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application. - Kailiang Huang; Xinlv Duan; Junxiao Feng; Ying Sun; Congyan Lu; Chuanke Chen; Guangfan Jiao; Xinpeng Lin; Jinhai Shao; Shihui Yin; Jiazhen Sheng; Zhaogui Wang; et al. (VLSI Technology and Circuits, 2022)

First Demonstration of High-Sensitivity (NEP 1fW1/2) Back-Illuminated Active-Matrix Deep UV Image Sensor by Monolithic Integration of Ga2O3 Photodetectors and Oxide Thin-Film-Transistors. - Yuan Qin; Congyan Lu; Zhaoan Yu; Zhihong Yao; Feihong Wu; Danian Dong; Xiaolong Zhao; Guangwei Xu; Yuhao Zhang; Shibing Long; Ling Li 013; Ming Liu 022 (VLSI Technology and Circuits, 2022)

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s). - Menggan Liu; Zhi Li 062; Wendong Lu; Kaifei Chen; Jiebin Niu; Fuxi Liao; Zijing Wu; Congyan Lu; Weizeng Li; Di Geng; Nianduan Lu; Chunmeng Dou; et al. (VLSI Technology and Circuits, 2024)