A single-chip CMOS UHF RFID Reader transceiver for mobile applications. - Le Ye; Huailin Liao; Fei Song; Jiang Chen; Congyin Shi; Chen Li 014; Junhua Liu; Ru Huang 001; Jinshu Zhao; Huiling Xiao; Ruiqiang Liu; Xinan Wang (ESSCIRC, 2009)

A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications. - Le Ye; Huailin Liao; Fei Song; Jiang Chen; Chen Li 014; Jinshu Zhao; Ruiqiang Liu; Chuan Wang; Congyin Shi; Junhua Liu; Ru Huang 001; Yangyuan Wang (IEEE J. Solid State Circuits, 2010)

-99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver. - Congyin Shi; Chuan Wang; Le Ye; Huailin Liao (ISCAS, 2011)

A 0.47mW 6th-order 20MHz active filter using highly power-efficient Opamp. - Le Ye; Congyin Shi; Huailin Liao; Ru Huang 001 (ISCAS, 2011)

A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process. - Junhua Liu; Chen Li 014; Long Chen 009; Congyin Shi; Xuankai Weng; Yixiao Wang; Jiayi Wang; Yu Liao; Le Ye; Huailin Liao; Ru Huang 001 (Sci. China Inf. Sci., 2013)

Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps. - Le Ye; Congyin Shi; Huailin Liao; Ru Huang 001; Yangyuan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 4.2 mm2 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS. - Long Chen 009; Yixiao Wang; Chuan Wang; Jiayi Wang; Congyin Shi; Xuankai Weng; Le Ye; Junhua Liu; Huailin Liao; Yangyuan Wang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Built-In Self Optimization for Variation Resilience of Analog Filters. - Jiafan Wang 002; Congyin Shi; Edgar Sánchez-Sinencio; Jiang Hu (ISVLSI, 2015)

150-850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization. - Congyin Shi; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Thwarting analog IC piracy via combinational locking. - Jiafan Wang 002; Congyin Shi; Adriana C. Sanabria-Borbon; Edgar Sánchez-Sinencio; Jiang Hu (ITC, 2017)

On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture. - Congyin Shi; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2017)

A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits. - Congyin Shi; Sanghoon Lee 008; Sergio Soto Aguilar; Edgar Sánchez-Sinencio (J. Electron. Test., 2018)

A Built-In Self-Test and In Situ Analog Circuit Optimization Platform. - Sanghoon Lee 008; Congyin Shi; Jiafan Wang 002; Adriana C. Sanabria-Borbon; Hatem Osman; Jiang Hu; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation. - Congyin Shi; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)