Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (ARVLSI, 2001)

A True Single-Phase 8-bit Adiabatic Multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (DAC, 2001)

A resonant clock generator for single-phase adiabatic systems. - Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 2001)

Energy recovering static memory. - Joohee Kim; Conrad H. Ziesler; Marios C. Papaefthymiou (ISLPED, 2002)

A 225 MHz resonant clocked ASIC chip. - Conrad H. Ziesler; Joohee Kim; Visvesh S. Sathe 001; Marios C. Papaefthymiou (ISLPED, 2003)

Energy Recovering ASIC Design. - Conrad H. Ziesler; Joohee Kim; Marios C. Papaefthymiou (ISVLSI, 2003)

Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. - Dan Ernst; Nam Sung Kim; Shidhartha Das; Sanjay Pant; Rajeev R. Rao; Toan Pham; Conrad H. Ziesler; David T. Blaauw; Todd M. Austin; Krisztián Flautner; Trevor N. Mudge (MICRO, 2003)

A clockless future for systems on chip. - Suhwan Kim 001; Conrad H. Ziesler (IEEE Des. Test Comput., 2003)

Fine-grain real-time reconfigurable pipelining. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IBM J. Res. Dev., 2003)

A true single-phase energy-recovery multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Empirical evaluation of timing and power in resonant clock distribution. - Juang-Ying Chueh; Conrad H. Ziesler; Marios C. Papaefthymiou (ISCAS (2), 2004)

Experimental Evaluation of Resonant Clock Distribution. - Juang-Ying Chueh; Conrad H. Ziesler; Marios C. Papaefthymiou (ISVLSI, 2004)

Fixed-Load Energy Recovery Memory for Low Power. - Joohee Kim; Conrad H. Ziesler (ISVLSI, 2004)

A synchronous interface for SoCs with multiple clock domains. - Visvesh S. Sathe 001; Conrad H. Ziesler; Marios C. Papaefthymiou; Suhwan Kim 001; Stephen V. Kosonocky (SoCC, 2004)

Energy recovering pipelines. - Conrad H. Ziesler (2004)

Fast, efficient, recovering, and irreversible. - Visvesh S. Sathe 001; Juang-Ying Chueh; Joohee Kim; Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (Conf. Computing Frontiers, 2005)

A GHz-class charge recovery logic. - Visvesh S. Sathe 001; Marios C. Papaefthymiou; Conrad H. Ziesler (ISLPED, 2005)

Two-Phase Resonant Clock Distribution. - Juang-Ying Chueh; Marios C. Papaefthymiou; Conrad H. Ziesler (ISVLSI, 2005)

Boost Logic: A High Speed Energy Recovery Circuit Family. - Visvesh S. Sathe 001; Marios C. Papaefthymiou; Conrad H. Ziesler (ISVLSI, 2005)

Charge-Recovery Computing on Silicon. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IEEE Trans. Computers, 2005)