Constraint optimization algorithms for digital image reconstruction from projections. - Constantinos E. Goutis (1978)

An optimal technique for tomographic image reconstruction from curved ray projections. - Constantinos E. Goutis; Tariq S. Durrani (ICASSP, 1982)

Reconstruction algorithms for limited view projection data. - Constantinos E. Goutis; Richard M. Leahy; S. Drossos (ICASSP, 1983)

Spectra using data distribution and covariance modelling. - Costas E. Goutis; Richard M. Leahy; P. G. Cassidy (ICASSP, 1984)

Tomographic and spectral analysis using noise statistics. - Richard M. Leahy; Constantinos E. Goutis; S. Drossos (ICASSP, 1984)

2-D Array processor having a controlled pipelined architecture for elliptical sparse matrices. - Costas E. Goutis; J. S. Sheblee; G. Russell (ICASSP, 1985)

Detection algorithms based on prediction error - additive noise - data orthogonality. - M. K. Ibrahim; Costas E. Goutis (ICASSP, 1985)

Optimal techniques for constraint based signal restoration and image reconstruction. - Richard M. Leahy; Costas E. Goutis (ICASSP, 1985)

An optimal technique for constraint-based image restoration and reconstruction. - Richard M. Leahy; Constantinos E. Goutis (IEEE Trans. Acoust. Speech Signal Process., 1986)

A generator for a number format conversion IC. - N. A. Kyrloglou; Odysseas G. Koufopavlou; Costas E. Goutis (Microprocessing and Microprogramming, 1990)

A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms. - Dimitris E. Metafas; Costas E. Goutis (Microprocessing and Microprogramming, 1990)

Direct mapping of nested loops on piecewise regular processor arrays. - Dimitrios Soudris; Michael K. Birbas; Constantinos E. Goutis (Algorithms and Parallel VLSI Architectures, 1991)

A placing and routing tool implemented in Prolog. - N. A. Kyrloglou; S. Koutroubinas; A. Koyandis; Constantinos E. Goutis (Microprocessing and Microprogramming, 1991)

Array processor for LS FIR system identification. - Spiros Nikolaidis 001; Odysseas G. Koufopavlou; Sergios Theodoridis; Constantinos E. Goutis (Microprocessing and Microprogramming, 1991)

Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations. - Dimitrios J. Soudris; Michael K. Birbas; Costas E. Goutis (Microprocessing and Microprogramming, 1991)

A processor for time-varying digital audio filters with special transition properties. - Spiridon Nikolaidis 001; John Mourjopoulos; Constantinos E. Goutis (RTS, 1992)

Image reconstruction on a special purpose array processor. - Odysseas G. Koufopavlou; Constantinos E. Goutis (Image Vis. Comput., 1992)

A Systematic Partitioning Method for Designing Fixed-Size Processor Arrays. - Efstathios D. Kyriakis-Bitzaros; Constantinos E. Goutis (J. Circuits Syst. Comput., 1992)

An Efficient Decompostion Technique for Mapping Nested Loops with Constant Dependencies into Regular Processor Arrays. - Efstathios D. Kyriakis-Bitzaros; Constantinos E. Goutis (J. Parallel Distributed Comput., 1992)

A VLSI synthesis tool for complementary output delta modulation FIR filters. - S. L. Horianopoulos; D. E. Metafas; Costas E. Goutis; Theodore L. Deliyannis (Microprocess. Microprogramming, 1992)

Systematic design of full adder-based architectures for convolution. - Dimitrios Soudris; Vassilis Paliouras; Thanos Stouraitis; Alexander Skavantzos; Constantinos E. Goutis (ICASSP (1), 1993)

Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays. - Efstathios D. Kyriakis-Bitzaros; Odysseas G. Koufopavlou; Constantinos E. Goutis (ICPP (3), 1993)

CORDIC Based Pipeline Architecture for All-pass Filters. - Spiridon Nikolaidis 001; D. E. Metafas; Constantinos E. Goutis (ISCAS, 1993)

A Systematic Methodology for Designing Multilevel Systolic Architectures. - Dimitrios Soudris; P. D. Georgakopoulos; Constantinos E. Goutis (ISCAS, 1993)

Development of a technology independent library. - George-Peter K. Economou; Spiridon Nikolaidis 001; D. E. Metafas; Constantinos E. Goutis (Microprocess. Microprogramming, 1993)

Implementation of Given's Rotation processors for DSP real-time applications. - D. E. Metafas; Evaggelinos P. Mariatos; Spiridon Nikolaidis 001; Constantinos E. Goutis (Microprocess. Microprogramming, 1993)

Real time Cepstrum computation based on an Advanced CORDIC processor. - D. E. Metafas; Spiridon Nikolaidis 001; Constantinos E. Goutis (Microprocess. Microprogramming, 1993)

A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules. - John Ant. Hallas; Evaggelinos P. Mariatos; Michael K. Birbas; Alexios N. Birbas; Constantinos E. Goutis (FPL, 1994)

Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic Notions and the Binary Arithmetic Coder (Q-Coder). - John Ant. Hallas; Michael K. Birbas; Alexios N. Birbas; John C. Kikidis; Constantinos E. Goutis (ISCAS, 1994)

A Fast DCT Processor, Based on Special Purpose CORDIC Rotators. - Evaggelinos P. Mariatos; D. E. Metafas; John Ant. Hallas; Constantinos E. Goutis (ISCAS, 1994)

Image coding using vector quantization of wavelet coefficients. - Chrissavgi Dre; George Branis; Costas E. Goutis (Microprocess. Microprogramming, 1994)

Experiences accumulated working towards medical decision support systems. - George-Peter K. Economou; N. M. Economopoulos; Dimitris K. Lymberopoulos; Constantinos E. Goutis (Microprocess. Microprogramming, 1994)

A bit-serial VLSI architecture for the 2-D discrete cosine transform. - Anna Tatsaki; Costas E. Goutis (Microprocess. Microprogramming, 1994)

Array processor for block adaptive LS FIR filtering. - Spiridon Nikolaidis 001; Sergios Theodoridis; Constantinos E. Goutis (Signal Process., 1994)

Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis. - George-Peter K. Economou; John Ant. Hallas; Evaggelinos P. Mariatos; Constantinos E. Goutis (ED&TC, 1995)

Alternative Architectures for the 2-D DCT Algorithm. - Chrissavgi Dre; Anna Tatsaki; Thanos Stouraitis; Constantinos E. Goutis (ISCAS, 1995)

An ANNs-based system for the diagnosis and treatment of diseases. - George-Peter K. Economou; Dimitris K. Lymberopoulos; Costas E. Goutis (Neural Process. Lett., 1995)

On the computation of the prime factor DST. - Anna Tatsaki; Chrissavgi Dre; Thanos Stouraitis; Costas E. Goutis (Signal Process., 1995)

Prime-factor DCT algorithms. - Anna Tatsaki; Chrissavgi Dre; Thanos Stouraitis; Costas E. Goutis (IEEE Trans. Signal Process., 1995)

A floating-point advanced cordic processor. - D. E. Metafas; Constantinos E. Goutis (J. VLSI Signal Process., 1995)

Accurate timing model for the CMOS inverter. - Labros Bisdounis; Spiros Nikolaidis 001; Odysseas G. Koufopavlou; Costas E. Goutis (ICECS, 1996)

Low-power image decoding using fractals. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Costas E. Goutis (ICECS, 1996)

A novel approach for reducing the switching activity in two-level logic circuits. - George Theodoridis; S. Theoharis; Dimitrios Soudris; Odysseas G. Koufopavlou; Costas E. Goutis (ICECS, 1996)

Transformation of Nested Loops into Uniform Recurrences and their Mapping to Regular Processor Arrays. - Efstathios D. Kyriakis-Bitzaros; Dimitrios Soudris; Constantinos E. Goutis (J. Circuits Syst. Comput., 1996)

Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. - Labros Bisdounis; Odysseas G. Koufopavlou; Constantinos E. Goutis; Spiridon Nikolaidis 001 (DATE, 1998)

Low-power implementation of discrete wavelet transform. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (EUSIPCO, 1998)

Novel codebook generation algorithms for vector quantization image compression. - Konstantinos Masselos; Thanos Stouraitis; Costas E. Goutis (ICASSP, 1998)

A novel algorithm for low-power image and video coding. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (IEEE Trans. Circuits Syst. Video Technol., 1998)

Trade-Off Analysis of a Low-Power Image Coding Algorithm. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (J. VLSI Signal Process., 1998)

Hardware and Power Requirements of Self-checking circuits. - A. P. Kakaroudas; Kyriakos Papadomanolakis; E. Karaolis; Spiros Nikolaidis 001; Nikolaos Alachiotis 002; Costas E. Goutis (ICECS, 1999)

Fault secure binary counter design. - E. Karaolis; Spiros Nikolaidis 001; Costas E. Goutis (ICECS, 1999)

System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors. - Kostas Masselos; Francky Catthoor; Costas E. Goutis; H. DeMan (ICECS, 1999)

Low power synthesis of sum-of-product computation in DSP algorithms. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (ISCAS (6), 1999)

The VLSI implementation of a baseband receiver for DECT-based portable applications. - M. Perakis; A. E. Tzimas; E. G. Metaxakis; Dimitrios Soudris; Grigorios A. Kalivas; C. Katis; Chrissavgi Dre; Constantinos E. Goutis; Adonios Thanailakis; Thanos Stouraitis (ISCAS (1), 1999)

An efficient probabilistic method for logic circuits using real delay gate model. - George Theodoridis; S. Theoharis; Dimitrios Soudris; Thanos Stouraitis; Constantinos E. Goutis (ISCAS (1), 1999)

Power exploration of multimedia applications realized on embedded cores. - Nikolaos D. Zervas; Kostas Masselos; Odysseas G. Koufopavlou; Constantinos E. Goutis (ISCAS (4), 1999)

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. - Kostas Masselos; Koen Danckaert; Francky Catthoor; Constantinos E. Goutis; Hugo De Man (ISLPED, 1999)

Strategy for power-efficient design of parallel systems. - Koen Danckaert; Kostas Masselos; Francky Catthoor; Hugo De Man; Constantinos E. Goutis (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Computation Reordering: A Novel Transformation for Low Power DSP Synthesis. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (VLSI Design, 1999)

A New Method for Low Power Design of Two-Level Logic Circuits. - George Theodoridis; Spyros Theoharis; Dimitrios Soudris; Constantinos E. Goutis (VLSI Design, 1999)

A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays. - Efstathios D. Kyriakis-Bitzaros; Constantinos E. Goutis (J. VLSI Signal Process., 1999)

Low power design of a multi-mode transceiver. - Dimitrios Soudris; Minas Perakis; Haris Mizas; Vasilios A. Mardiris; Kosfas Katis; Chrissavgi Dre; A. E. Tzimas; E. G. Metaxakis; Grigorios Kalivas; Nikolaos D. Zervas; Spyros Theoharis; George Theodoridis; et al. (ISCAS, 2000)

A methodology for the behavioral-level event-driven power management of digital receivers. - Nikolaos D. Zervas; Dimitrios Soudris; Spyros Theoharis; Constantinos E. Goutis; Adonios Thanailakis (ISCAS, 2000)

Low power synthesis of sum-of-products computation (poster session). - Kostas Masselos; S. Theoharis; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (ISLPED, 2000)

Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. - Athanasios Kakarountas; Kyriakos Papadomanolakis; Vasileios Kokkinos; Constantinos E. Goutis (PATMOS, 2000)

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. - Dimitrios Soudris; Nikolaos D. Zervas; Antonios Argyriou; Minas Dasygenis; Konstantinos Tatas; Constantinos E. Goutis; Adonios Thanailakis (PATMOS, 2000)

Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. - George Theodoridis; S. Theoharis; Nikolaos D. Zervas; Constantinos E. Goutis (PATMOS, 2000)

Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. - Nikolaos D. Zervas; S. Theoharis; Athanasios Kakarountas; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (PATMOS, 2000)

Low power architectures for digital signal processing. - Kostas Masselos; Panagiotis Merakos; Thanos Stouraitis; Constantinos E. Goutis (J. Syst. Archit., 2000)

A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints. - Kostas Masselos; Koen Danckaert; Francky Catthoor; Nikolaos D. Zervas; Constantinos E. Goutis; Hugo De Man (J. VLSI Signal Process., 2000)

A wavelet-tree image coding system with efficient memory utilization. - Yiannis Andreopoulos; Peter Schelkens; Nikolaos D. Zervas; Thanos Stouraitis; Costas E. Goutis; Jan Cornelis 001 (ICASSP, 2001)

Quantization effect on VLSI implementations for the 9/7 DWT filters. - Vassilis Spiliotopoulos; Nikolaos D. Zervas; Yiannis Andreopoulos; Giorgos P. Anagnostopoulos; Costas E. Goutis (ICASSP, 2001)

Design of low-power on-line reconfigurable datapaths using self-checking circuits. - Athanasios P. Kakarountas; Vasileios Kokkinos; Costas E. Goutis (ICECS, 2001)

A code transformation-based methodology for improving I-cache performance. - Nikolaos D. Liveris; Nikolaos D. Zervas; A. P. Kakaroudas; Costas E. Goutis (ICECS, 2001)

Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures. - Kostas Masselos; Francky Catthoor; A. Kakarudas; Costas E. Goutis; Hugo De Man (ICECS, 2001)

A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition. - Yiannis Andreopoulos; Nikolaos D. Zervas; Gauthier Lafruit; Peter Schelkens; Thanos Stouraitis; Costas E. Goutis; Jan Cornelis 001 (ICIP (3), 2001)

Power, performance and area exploration of block matching algorithms mapped on programmable processors. - Nikolas Kroupis; Minas Dasygenis; Antonios Argyriou; Konstantinos Tatas; Dimitrios Soudris; Antonios Thanailakis; Nikolaos D. Zervas; Constantinos E. Goutis (ICIP (3), 2001)

Performance comparison of DWT scheduling alternatives on programmable platforms. - Nikolaos D. Zervas; I. Tagopoulos; Vassilis Spiliotopoulos; Giorgos P. Anagnostopoulos; Dimitrios Soudris; Constantinos E. Goutis (ISCAS (2), 2001)

Evaluation of design alternatives for the 2-D-discrete wavelet transform. - Nikolaos D. Zervas; Giorgos P. Anagnostopoulos; Vassilis Spiliotopoulos; Yiannis Andreopoulos; Costas E. Goutis (IEEE Trans. Circuits Syst. Video Technol., 2001)

A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. - George Theodoridis; Spyros Theoharis; Dimitrios Soudris; Constantinos E. Goutis (VLSI Design, 2001)

A Fast and Accurate Method of Power Estimation for Logic Level Networks. - George Theodoridis; S. Theoharis; Dimitrios Soudris; Constantinos E. Goutis (VLSI Design, 2001)

A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. - Nikolaos D. Liveris; Nikolaos D. Zervas; Dimitrios Soudris; Constantinos E. Goutis (DATE, 2002)

An efficient VLSI implementation for forward and inverse wavelet transform for JPEG2000. - Grigoris Dimitroulakos; Nikolaos D. Zervas; Nicolas Sklavos 001; Costas E. Goutis (DSP, 2002)

A low power fault secure timer implementation based on the Gray encoding scheme. - Kyriakos S. Papadomanolakis; Athanasios P. Kakarountas; Nicolas Sklavos 001; Costas E. Goutis (ICECS, 2002)

Confronting violations of the TSCG(T) in low-power design. - Athanasios Kakarountas; Kyriakos Papadomanolakis; Spiridon Nikolaidis 001; Dimitrios Soudris; Constantinos E. Goutis (ISCAS (4), 2002)

Power Efficient Vector Quantization Design Using Pixel Truncation. - Kostas Masselos; Panagiotis Merakos; Constantinos E. Goutis (PATMOS, 2002)

A fast and accurate delay dependent method for switching estimation of large combinational circuits. - S. Theoharis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis; Adonios Thanailakis (J. Syst. Archit., 2002)

Memory accesses reordering for interconnect power reduction in sum-of-products computations. - Konstantinos Masselos; Spyros Theoharis; Panagiotis Merakos; Thanos Stouraitis; Costas E. Goutis (IEEE Trans. Signal Process., 2002)

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. - Kostas Masselos; Francky Catthoor; Constantinos E. Goutis; Hugo De Man (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Power Efficient Hierarchical Scheduling for DSP Transformations. - Panagiotis K. Merakos; Konstantinos Masselos; Constantinos E. Goutis (VLSI Design, 2002)

Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores. - Nikolaos D. Zervas; Konstantinos Masselos; Yorgos A. Karayiannis; Costas E. Goutis (VLSI Design, 2002)

Power aware data type refinement on the HIPERLAN/2. - Gregory Dimitroulakos; Athanasios Milidonis; Michalis D. Galanis; George Theodoridis; Costas E. Goutis; Francky Catthoor (ICECS, 2003)

A novel high-speed counter with counting rate independent of the counter's length. - Athanasios P. Kakarountas; George Theodoridis; Kyriakos S. Papadomanolakis; Costas E. Goutis (ICECS, 2003)

Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications. - Kostas Masselos; Francky Catthoor; Constantinos E. Goutis; Hugo De Man (Des. Autom. Embed. Syst., 2003)

A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits. - Spiridon Nikolaidis 001; E. Karaolis; Athanasios Kakarountas; Kyriakos Papadomanolakis; Constantinos E. Goutis (J. Circuits Syst. Comput., 2003)

Power efficient data path synthesis of sum-of-products computations. - Kostas Masselos; Panagiotis Merakos; S. Theoharis; Thanos Stouraitis; Constantinos E. Goutis (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (DATE, 2004)

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FCCM, 2004)

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FPGA, 2004)

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FPL, 2004)

Comparison of the hardware architectures and FPGA implementations of stream ciphers. - Michalis D. Galanis; Paris Kitsos; Giorgos Kostopoulos; Nicolas Sklavos 001; Odysseas G. Koufopavlou; Costas E. Goutis (ICECS, 2004)

A high performance data-path to accelerate DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Costas E. Goutis (ICECS, 2004)

Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function. - Harris E. Michail; Athanasios P. Kakarountas; Athanasios Milidonis; Costas E. Goutis (ICECS, 2004)

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (PATMOS, 2004)

The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems. - Athanasios Kakarountas; Vassilis Spiliotopoulos; Spiridon Nikolaidis 001; Constantinos E. Goutis (PATMOS, 2004)

A Novel Constant-Time Fault-Secure Binary Counter. - Dimitris Karatasos; Athanasios Kakarountas; George Theodoridis; Constantinos E. Goutis (PATMOS, 2004)

A Novel Data-Path for Accelerating DSP Kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Costas E. Goutis (SAMOS, 2004)

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. - Athanasios Milidonis; Grigoris Dimitroulakos; Michalis D. Galanis; George Theodoridis; Constantinos E. Goutis; Francky Catthoor (SCOPES, 2004)

A Framework for Data Partitioning for C++ Data-Intensive Applications. - Athanasios Milidonis; Gregory Dimitroulakos; Michalis D. Galanis; Athanasios P. Kakarountas; George Theodoridis; Constantinos E. Goutis; Francky Catthoor (Des. Autom. Embed. Syst., 2004)

Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors. - Kostas Masselos; Francky Catthoor; Constantinos E. Goutis; Hugo De Man (J. VLSI Signal Process., 2004)

Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays. - Grigoris Dimitroulakos; Michalis D. Galanis; Costas E. Goutis (ASAP, 2005)

Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (ASAP, 2005)

Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (FCCM, 2005)

Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs. - Grigoris Dimitroulakos; Michalis D. Galanis; Costas E. Goutis (FPL, 2005)

Partitioning DSP applications to different granularity reconfigurable hardware. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (ICECS, 2005)

Novel high throughput implementation of SHA-256 hash function through pre-computation technique. - Harris E. Michail; Athanasios Milidonis; Athanasios Kakarountas; Constantinos E. Goutis (ICECS, 2005)

A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures. - Grigoris Dimitroulakos; Michalis D. Galanis; Costas E. Goutis (IPDPS, 2005)

A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (IPDPS, 2005)

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard. - Grigoris Dimitroulakos; Michalis D. Galanis; Costas E. Goutis; Athanasios Milidonis (ISCAS (1), 2005)

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays. - Michalis D. Galanis; Gregory Dimitroulakos; Constantinos E. Goutis (ISCAS (4), 2005)

A methodology for partitioning DSP applications in hybrid reconfigurable systems. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (ISCAS (2), 2005)

A low-power and high-throughput implementation of the SHA-1 hash function. - Haralambos Michail; Athanasios P. Kakarountas; Odysseas G. Koufopavlou; Constantinos E. Goutis (ISCAS (4), 2005)

Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (PATMOS, 2005)

Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. - Haralambos Michail; Athanasios Kakarountas; George N. Selimis; Costas E. Goutis (PATMOS, 2005)

A method for partitioning applications in hybrid reconfigurable architectures. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Costas E. Goutis (Des. Autom. Embed. Syst., 2005)

Comparison of the Hardware Implementation of Stream Ciphers. - Michalis D. Galanis; Paris Kitsos; Giorgos Kostopoulos; Nicolas Sklavos 001; Constantinos E. Goutis (Int. Arab J. Inf. Technol., 2005)

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000. - Grigoris Dimitroulakos; Michalis D. Galanis; Athanasios Milidonis; Constantinos E. Goutis (Integr., 2005)

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Constantinos E. Goutis (J. Circuits Syst. Comput., 2005)

Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core. - Harris E. Michail; Athanasios P. Kakarountas; Athanasios Milidonis; George A. Panagiotakopoulos; Vasilis N. Thanasoulis; Costas E. Goutis (ICECS, 2006)

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures. - Grigoris Dimitroulakos; Michalis D. Galanis; Constantinos E. Goutis (IPDPS, 2006)

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic. - Michalis D. Galanis; Grigoris Dimitroulakos; Constantinos E. Goutis (IPDPS, 2006)

Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware. - Michalis D. Galanis; Grigoris Dimitroulakos; Constantinos E. Goutis (IPDPS, 2006)

Resource constrained modulo scheduling for coarse-grained reconfigurable arrays. - Grigoris Dimitroulakos; Michalis D. Galanis; Constantinos E. Goutis (ISCAS, 2006)

Mapping DSP applications on processor/coarse-grain reconfigurable array architectures. - Michalis D. Galanis; Grigoris Dimitroulakos; Constantinos E. Goutis (ISCAS, 2006)

Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path. - Michalis D. Galanis; Gregory Dimitroulakos; Costas E. Goutis (ICSAMOS, 2006)

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems. - Michalis D. Galanis; Athanasios Milidonis; Athanasios Kakarountas; Costas E. Goutis (Microelectron. J., 2006)

A high-performance data path for synthesizing DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Constantinos E. Goutis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (J. Supercomput., 2006)

Partitioning Methodology for Heterogeneous Reconfigurable Functional Units. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (J. Supercomput., 2006)

High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. - Athanasios Kakarountas; Haralambos Michail; Athanasios Milidonis; Costas E. Goutis; George Theodoridis (J. Supercomput., 2006)

A unified evaluation framework for coarse grained reconfigurable array architectures. - Grigoris Dimitroulakos; Michalis D. Galanis; Nikos Kostaras; Costas E. Goutis (Conf. Computing Frontiers, 2007)

Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. - Athanasios Milidonis; Nikolaos Alachiotis 002; Vasileios Porpodas; Haralambos Michail; Athanasios Kakarountas; Constantinos E. Goutis (DATE, 2007)

Implementation of HSSec: a high-speed cryptographic co-processor. - Athanasios P. Kakarountas; Haralambos Michail; Costas E. Goutis; Costas Efstathiou (ETFA, 2007)

Compiler assisted architectural exploration for coarse grained reconfigurable arrays. - Grigoris Dimitroulakos; Nikos Kostaras; Michalis D. Galanis; Costas E. Goutis (ACM Great Lakes Symposium on VLSI, 2007)

Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (ACM Great Lakes Symposium on VLSI, 2007)

Throughput Optimization of the Cipher Message Authentication Code. - Harris E. Michail; Athanasios P. Kakarountas; Georgios N. Selimis; Constantinos E. Goutis (DSP, 2007)

Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (IPDPS, 2007)

Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (PATMOS, 2007)

Server side hashing core exceeding 3 Gbps of throughput. - Harris E. Michail; George A. Panagiotakopoulos; Vasilis N. Thanasoulis; Athanasios Kakarountas; Costas E. Goutis (Int. J. Secur. Networks, 2007)

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (Microprocess. Microsystems, 2007)

Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture. - Grigoris Dimitroulakos; Michalis D. Galanis; Costas E. Goutis (J. Supercomput., 2007)

Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (J. Supercomput., 2007)

Speedups in embedded systems with a high-performance coprocessor datapath. - Michalis D. Galanis; Gregory Dimitroulakos; Spyros Tragoudas; Costas E. Goutis (ACM Trans. Design Autom. Electr. Syst., 2007)

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System. - Michalis D. Galanis; Grigoris Dimitroulakos; Costas E. Goutis (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays. - Stavros Georgiopoulos; Grigoris Dimitroulakos; Costas E. Goutis (SoC, 2008)

Novel Hardware Implementation of the Cipher Message Authentication Code. - Harris E. Michail; Georgios N. Selimis; Michalis D. Galanis; Dimitrios M. Schinianakis; Constantinos E. Goutis (J. Comput. Networks Commun., 2008)

Efficient high-performance implementation of JPEG-LS encoder. - Markos E. Papadonikolakis; Athanasios P. Kakarountas; Costas E. Goutis (J. Real Time Image Process., 2008)

Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path. - Michalis D. Galanis; Costas E. Goutis (J. Syst. Archit., 2008)

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path. - Michalis D. Galanis; Gregory Dimitroulakos; Costas E. Goutis (J. Signal Process. Syst., 2008)

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse. - Athanasios Milidonis; Vasileios Porpodas; Nikolaos Alachiotis 002; Athanasios P. Kakarountas; Harris E. Michail; George A. Panagiotakopoulos; Costas E. Goutis (IET Comput. Digit. Tech., 2009)

Resource aware mapping on coarse grained reconfigurable arrays. - Grigoris Dimitroulakos; Stavros Georgiopoulos; Michalis D. Galanis; Costas E. Goutis (Microprocess. Microsystems, 2009)

A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores. - Harris E. Michail; Athanasios Kakarountas; Athanasios Milidonis; Costas E. Goutis (IEEE Trans. Dependable Secur. Comput., 2009)

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays. - Grigoris Dimitroulakos; Nikos Kostaras; Michalis D. Galanis; Costas E. Goutis (J. Supercomput., 2009)

Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor. - Harris E. Michail; George Athanasiou; George Makridakis; Costas E. Goutis (ICECS, 2010)

Exploration of cryptographic ASIP designs for wireless sensor nodes. - Ioanna Tsekoura; Georgios N. Selimis; Jos Hulzink; Francky Catthoor; Jos Huisken; Harmke de Groot; Constantinos E. Goutis (ICECS, 2010)

Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign. - Harris E. Michail; George Athanasiou; Angeliki Kritikakou; Costas E. Goutis; Andreas Gregoriades; Vicky G. Papadopoulou (SECRYPT, 2010)

Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy. - Athanasios Milidonis; Nikolaos Alachiotis 002; Vasileios Porpodas; Harris E. Michail; George A. Panagiotakopoulos; Athanasios P. Kakarountas; Costas E. Goutis (J. Signal Process. Syst., 2010)

Cipher Block Based Authentication Module: a Hardware Design Perspective. - Harris E. Michail; Dimitrios M. Schinianakis; Costas E. Goutis; Athanasios P. Kakarountas; Georgios N. Selimis (J. Circuits Syst. Comput., 2011)

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization. - Vasilios I. Kelefouras; George Athanasiou; Nikolaos Alachiotis 002; Harris E. Michail; Angeliki Kritikakou; Costas E. Goutis (IEEE Trans. Signal Process., 2011)

A template-based methodology for efficient microprocessor and FPGA accelerator co-design. - Angeliki Kritikakou; Francky Catthoor; George Athanasiou; Vasilios I. Kelefouras; Costas E. Goutis (ICSAMOS, 2012)

High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. - George Athanasiou; Chara I. Chalkou; D. Bardis; Harris E. Michail; George Theodoridis; Costas E. Goutis (SECRYPT, 2012)

On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. - Harris E. Michail; George Athanasiou; Andreas Gregoriades; George Theodoridis; Costas E. Goutis (SECRYPT, 2012)

A data locality methodology for matrix-matrix multiplication algorithm. - Nikolaos Alachiotis 002; Vasilios I. Kelefouras; George Athanasiou; Harris E. Michail; Angeliki Kritikakou; Costas E. Goutis (J. Supercomput., 2012)

On the exploitation of a high-throughput SHA-256 FPGA design for HMAC. - Harris E. Michail; George Athanasiou; Vasilios I. Kelefouras; George Theodoridis; Costas E. Goutis (ACM Trans. Reconfigurable Technol. Syst., 2012)

A systematic approach to classify design-time global scheduling techniques. - Angeliki Kritikakou; Francky Catthoor; Vasilios I. Kelefouras; Costas E. Goutis (ACM Comput. Surv., 2013)

High-performance FPGA implementations of the cryptographic hash function JH. - George Athanasiou; Harris E. Michail; George Theodoridis; Costas E. Goutis (IET Comput. Digit. Tech., 2013)

A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. - George Athanasiou; George Theodoridis; Costas E. Goutis; Harris E. Michail; Takis Kasparis (J. Circuits Syst. Comput., 2013)

Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints. - Angeliki Kritikakou; Francky Catthoor; George Athanasiou; Vasilios I. Kelefouras; Costas E. Goutis (ACM Trans. Archit. Code Optim., 2013)

Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes. - Angeliki Kritikakou; Francky Catthoor; Vasilios I. Kelefouras; Costas E. Goutis (ACM Trans. Design Autom. Electr. Syst., 2013)

Optimising the SHA-512 cryptographic hash function on FPGAs. - Georgios Athanasiou; Harris E. Michail; George Theodoridis; Costas E. Goutis (IET Comput. Digit. Tech., 2014)

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. - Harris E. Michail; Georgios Athanasiou; George Theodoridis; Costas E. Goutis (Integr., 2014)

A scalable and near-optimal representation of access schemes for memory management. - Angeliki Kritikakou; Francky Catthoor; Vasilios I. Kelefouras; Costas E. Goutis (ACM Trans. Archit. Code Optim., 2014)

A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization. - Vasilios I. Kelefouras; Angeliki Kritikakou; Costas E. Goutis (J. Supercomput., 2014)

A Matrix-Matrix Multiplication methodology for single/multi-core architectures using SIMD. - Vasilios I. Kelefouras; Angeliki Kritikakou; Costas E. Goutis (J. Supercomput., 2014)

A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices. - Vasilios I. Kelefouras; Angeliki Kritikakou; Konstantinos Siourounis; Costas E. Goutis (J. Signal Process. Syst., 2014)

Hardware implementation of the Totally Self-Checking SHA-256 hash core. - Harris E. Michail; Apostolis Kotsiolis; Athanasios Kakarountas; George Athanasiou; Costas E. Goutis (EUROCON, 2015)

A methodology for speeding up loop kernels by exploiting the software information and the memory architecture. - Vasilios I. Kelefouras; Angeliki Kritikakou; Constantinos E. Goutis (Comput. Lang. Syst. Struct., 2015)

A methodology for speeding up matrix vector multiplication for single/multi-core architectures. - Vasilios I. Kelefouras; Angeliki Kritikakou; Elissavet Papadima; Constantinos E. Goutis (J. Supercomput., 2015)

Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. - Harris E. Michail; George Athanasiou; Vasilios I. Kelefouras; George Theodoridis; Thanos Stouraitis; Costas E. Goutis (J. Circuits Syst. Comput., 2016)

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. - Harris E. Michail; Georgios Athanasiou; George Theodoridis; Andreas Gregoriades; Costas E. Goutis (Microprocess. Microsystems, 2016)

Array Size Computation under Uniform Overlapping and Irregular Accesses. - Angeliki Kritikakou; Francky Catthoor; Vasilios I. Kelefouras; Costas E. Goutis (ACM Trans. Design Autom. Electr. Syst., 2016)