Verification by Simulation Comparison using Interface Synthesis. - Cordula Hansen; Arno Kunzmann; Wolfgang Rosenstiel (DATE, 1998)

An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications. - Cordula Hansen; Francisco Nascimento; Wolfgang Rosenstiel (DAC, 1999)

An Interface Description Model for Reuse of Algorithmic Hardware Specifications. - Cordula Hansen; Matthias Uhlmann; Wolfgang Rosenstiel (MBMV, 1999)

Transformation of algorithmic simulation vector sets considering mapping problems of I/O operations. - Cordula Hansen; Wolfgang Rosenstiel (HLDVT, 2000)

High Level Testbench Transformation for Pipelined Components. - Cordula Hansen; Wolfgang Rosenstiel (MBMV, 2002)