Comments, with reply, on 'Characterization and modeling of mismatch in MOS transistors for precision analog design'. - Cormac S. G. Conroy; William A. Lane; Michael A. Moran; Kadaba R. Lakshmikumar; Miles A. Copeland; Robert A. Hadaway (IEEE J. Solid State Circuits, 1988)

Statistical design techniques for D/A converters. - Cormac S. G. Conroy; William A. Lane; Michael A. Moran (IEEE J. Solid State Circuits, 1989)

An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS. - Cormac S. G. Conroy; David W. Cline; Paul R. Gray (IEEE J. Solid State Circuits, 1993)

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. - Sangjin Byun; Chan-Hong Park; Yongchul Song; Sung-Ho Wang; Cormac S. G. Conroy; Beomsup Kim (IEEE J. Solid State Circuits, 2003)

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. - Jinwook Kim; Jeongsik Yang; Sangjin Byun; Hyunduk Jun; Jeongkyu Park; Cormac S. G. Conroy; Beomsup Kim (IEEE J. Solid State Circuits, 2005)