Structured sampling and recovery of iEEG signals. - Luca Baldassarre; Cosimo Aprile; Mahsa Shoaran; Yusuf Leblebici; Volkan Cevher (CAMSAP, 2015)

A primal-dual framework for mixtures of regularizers. - Baran Gozcu; Luca Baldassarre; Quoc Tran-Dinh; Cosimo Aprile; Volkan Cevher (EUSIPCO, 2015)

A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. - Alessandro Cevrero; Cosimo Aprile; Pier Andrea Francese; Urs Bapst; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Hazar Yueksel; Ilter Oezkaya; Yusuf Leblebici; et al. (VLSIC, 2015)

Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition. - Cosimo Aprile; Luca Baldassarre; Vipul Gupta; Juhwan Yoo; Mahsa Shoaran; Yusuf Leblebici; Volkan Cevher (ACM Great Lakes Symposium on VLSI, 2016)

DCT Learning-Based Hardware Design for Neural Signal Acquisition Systems. - Cosimo Aprile; Johannes Wüthrich; Luca Baldassarre; Yusuf Leblebici; Volkan Cevher (Conf. Computing Frontiers, 2017)

An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems. - Cosimo Aprile; Johannes Wüthrich; Luca Baldassarre; Yusuf Leblebici; Volkan Cevher (CF, 2018)

Real-Time DCT Learning-based Reconstruction of Neural Signals. - Rabeeh Karimi Mahabadi; Cosimo Aprile; Volkan Cevher (EUSIPCO, 2018)

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Thomas Toifl; et al. (ISCAS, 2018)

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. - Cosimo Aprile; Alessandro Cevrero; Pier Andrea Francese; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Thomas Morf; Lukas Kull; Ilter Oezkaya; Yusuf Leblebici; Volkan Cevher; Thomas Toifl (IEEE J. Solid State Circuits, 2018)

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants. - Cosimo Aprile; Kerim Türe; Luca Baldassarre; Mahsa Shoaran; Gürkan Yilmaz; Franco Maloberti; Catherine Dehollain; Yusuf Leblebici; Volkan Cevher (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (A-SSCC, 2019)

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. - Jonathan Narinx; Robert Giterman; Andrea Bonetti; Nicolas Frigerio; Cosimo Aprile; Andreas Burg 001; Yusuf Leblebici (A-SSCC, 2019)

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. - Gain Kim; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; Hazar Yueksel; Cosimo Aprile; Thomas Morf; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; et al. (ISSCC, 2019)

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. - Gain Kim; Marcel A. Kossel; Alessandro Cevrero; Ilter Özkaya; Andreas Burg 001; Thomas Toifl; Yusuf Leblebici; Lukas Kull; Danny Luu; Matthias Braendli; Christian Menolfi; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2020)

A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS. - Arda Uran; Kerim Türe; Cosimo Aprile; Alix Trouillet; Florian Fallegger; Azita Emami; Stéphanie P. Lacour; Catherine Dehollain; Yusuf Leblebici; Volkan Cevher (CICC, 2021)

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS. - Arda Uran; Kerim Türe; Cosimo Aprile; Alix Trouillet; Florian Fallegger; Emilie C. M. Revol; Azita Emami; Stéphanie P. Lacour; Catherine Dehollain; Yusuf Leblebici; Volkan Cevher (IEEE J. Solid State Circuits, 2022)

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling. - Armin Tajalli; Cosimo Aprile; Milad Ataei; Rolf Beerwerth; Dario Carneli; Maik Fuhs; Kiarash Gharibdoust; Ali Hormati; James Hudner; Victor Perrin; Amin Shokrollahi; Richard Simpson 004; et al. (CICC, 2025)