Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. - Costas Argyrides; Hamid R. Zarandi; Dhiraj K. Pradhan (DFT, 2007)

Highly Reliable Power Aware Memory Design. - Costas Argyrides; Dhiraj K. Pradhan (IOLTS, 2007)

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Costas Argyrides; Dhiraj K. Pradhan (IPDPS, 2007)

Multiple Upsets Tolerance in SRAM Memory. - Costas Argyrides; Hamid R. Zarandi; Dhiraj K. Pradhan (ISCAS, 2007)

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Costas Argyrides; Dhiraj K. Pradhan (ISCAS, 2007)

A soft error robust and power aware memory design. - Costas Argyrides; Carlos Arthur Lang Lisbôa; Luigi Carro; Dhiraj K. Pradhan (SBCCI, 2007)

High defect tolerant low cost memory chips. - Costas Argyrides; Ahmad A. Al-Yamani; Dhiraj K. Pradhan (SoCC, 2007)

Improved decoding algorithm for high reliable reed muller coding. - Costas Argyrides; Dhiraj K. Pradhan (SoCC, 2007)

Yield improvement and power aware low cost memory chips. - Costas Argyrides; Stephania Loizidou Himona; Dhiraj K. Pradhan (WREFT@CF, 2008)

Multiple Event Upsets Aware FPGAs Using Protected Schemes. - Costas Argyrides; Dhiraj K. Pradhan (Fault-Tolerant Distributed Algorithms on VLSI Chips, 2008)

Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. - Costas Argyrides; Fabian Vargas 001; Marlon Moraes; Dhiraj K. Pradhan (IOLTS, 2008)

Area Reliability Trade-Off in Improved Reed Muller Coding. - Costas Argyrides; Stephania Loizidou; Dhiraj K. Pradhan (SAMOS, 2008)

Single Error Correcting Finite Field Multipliers Over GF(2m). - Jimson Mathew; Costas Argyrides; Abusaleh M. Jabir; Hafizur Rahaman 001; Dhiraj K. Pradhan (VLSI Design, 2008)

Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. - Carlos Arthur Lang Lisbôa; Costas Argyrides; Dhiraj K. Pradhan; Luigi Carro (VTS, 2008)

A fast error correction technique for matrix multiplication algorithms. - Costas Argyrides; Carlos Arthur Lang Lisbôa; Dhiraj K. Pradhan; Luigi Carro (IOLTS, 2009)

Increasing memory yield in future technologies through innovative design. - Costas Argyrides; Ahmad A. Al-Yamani; Carlos Arthur Lang Lisbôa; Luigi Carro; Dhiraj K. Pradhan (ISQED, 2009)

Single element correction in sorting algorithms with minimum delay overhead. - Costas Argyrides; Carlos Arthur Lang Lisbôa; Dhiraj K. Pradhan; Luigi Carro (LATW, 2009)

Reliability aware yield improvement technique for nanotechnology based circuits. - Costas Argyrides; Giorgos Dimosthenous; Dhiraj K. Pradhan; Carlos Arthur Lang Lisbôa; Luigi Carro (SBCCI, 2009)

Multiple Bit Error Detection and Correction in Memory. - J. F. Tarillo; Nikolaos Mavrogiannakis; Carlos Arthur Lang Lisbôa; Costas Argyrides; Luigi Carro (DSD, 2010)

Improving reliability for bit parallel finite field multipliers using Decimal Hamming. - Nikolaos Mavrogiannakis; Costas Argyrides; Dhiraj K. Pradhan (EWDTS, 2010)

Improved Yield in Nanotechnology Circuits Using Non-square Meshes. - Costas Argyrides; Nikolaos Mavrogiannakis; Dhiraj K. Pradhan (ISVLSI, 2010)

Evaluation of a new low cost software level fault tolerance technique to cope with soft errors. - Jimmy Tarrillo; Carlos Arthur Lang Lisbôa; Luigi Carro; Costas Argyrides; Dhiraj K. Pradhan (LATW, 2010)

Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors. - Costas Argyrides; Ronaldo Rodrigues Ferreira; Carlos Arthur Lang Lisbôa; Luigi Carro (DFT, 2011)

Fault Tolerant Single Error Correction Encoders. - Juan Antonio Maestro; Pedro Reviriego; Costas Argyrides; Dhiraj K. Pradhan (J. Electron. Test., 2011)

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction. - Costas Argyrides; Raul Chipana; Fabian Vargas 001; Dhiraj K. Pradhan (IEEE Trans. Reliab., 2011)

Matrix Codes for Reliable and Cost Efficient Memory Chips. - Costas Argyrides; Dhiraj K. Pradhan; Taskin Koçak (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Efficient error detection in Double Error Correction BCH codes for memory applications. - Pedro Reviriego; Costas Argyrides; Juan Antonio Maestro (Microelectron. Reliab., 2012)

Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors. - Costas Argyrides; Pedro Reviriego; Juan Antonio Maestro (IEEE Trans. Reliab., 2013)

Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs. - Hayk T. Grigoryan; Samvel K. Shoukourian; Gurgen Harutyunyan; Yervant Zorian; Costas Argyrides (ITC, 2018)

Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction. - Jiaqiang Li; Pedro Reviriego; Liyi Xiao; Costas Argyrides; Jie Li 030 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Efficient Concurrent Error Detection for SEC-DAEC Encoders. - Jiaqiang Li; Pedro Reviriego; Costas Argyrides; Liyi Xiao (IOLTS, 2019)

A Novel Protection Technique for Embedded Memories with Optimized PPA. - Costas Argyrides; Vilas Sridharan; Hayk Danoyan; Gurgen Harutyunyan; Yervant Zorian (ITC, 2022)

Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety. - Minqiang Peng; Youfa Wu; Jialiang Li; Alex Yu; Grigor Tshagharyan; Costas Argyrides; Vilas Sridharan; Gurgen Harutyunyan; Yervant Zorian; Nilanjan Mukherjee (VTS, 2022)

Utilizing ECC Analytics to Improve Memory Lifecycle Management. - Costas Argyrides; Grigor Tshagharyan; Gurgen Harutyunyan; Yervant Zorian (ITC, 2023)