IBM System z10 I/O subsystem. - Edward W. Chencinski; M. A. Check; Casimer M. DeCusatis; H. Deng; M. Grassi; Thomas A. Gregg; Markus M. Helms; A. D. Koenig; L. Mohr; Kulwant M. Pandey; Thomas Schlipf; Torsten Schober; et al. (IBM J. Res. Dev., 2009)

IBM System z10 processor cache subsystem microarchitecture. - Pak-kin Mak; Craig R. Walters; Gary E. Strait (IBM J. Res. Dev., 2009)

IBM zEnterprise 196 microprocessor and cache subsystem. - Fadi Busaba; Michael A. Blake; Brian W. Curran; Michael F. Fee; Christian Jacobi 002; Pak-kin Mak; Brian R. Prasky; Craig R. Walters (IBM J. Res. Dev., 2012)

Performance innovation in the IBM zEnterprise 196 processor. - Dan F. Greiner; Marcel M. Mitran; Timothy J. Slegel; Craig R. Walters; Charles F. Webb (IBM J. Res. Dev., 2012)

The IBM z13 processor cache subsystem. - Craig R. Walters; Pak-kin Mak; Deanna Postles Dunn Berger; Michael A. Blake; Tim Bronson; K. D. Klapproth; A. J. O'Neill; Robert J. Sonnelitter; Vesselina K. Papazova (IBM J. Res. Dev., 2015)

Performance innovations in the IBM z14 platform. - Craig R. Walters; David S. Hutton; Edward W. Chencinski; Christine Axnix; Ralf Winkelmann; Michael F. Fee; Anthony Saporito; Christian Jacobi 002 (IBM J. Res. Dev., 2018)

Design of the IBM z15 microprocessor. - Anthony Saporito; Martin Recktenwald; Christian Jacobi 002; Gerrit Koch; Deanna Postles Dunn Berger; Robert J. Sonnelitter; Craig R. Walters; Jang-Soo Lee; Cédric Lichtenau; Ulrich Mayer; Eduard Herkel; Stefan Payer; et al. (IBM J. Res. Dev., 2020)

Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability. - Deanna Postles Dunn Berger; Christian Jacobi 002; Craig R. Walters; Robert J. Sonnelitter; Mike Cadigan; Matthias Klein (IEEE Micro, 2023)

Enterprise-Class Cache Compression Design. - Alper Buyuktosunoglu; David Trilla; Bülent Abali; Deanna Postles Dunn Berger; Craig R. Walters; Jang-Soo Lee (HPCA, 2024)

IBM z16 Modular Scalable Cache Hierarchy and Future Concept Applications. - Craig R. Walters (MWSCAS, 2024)

Enterprise Class Modular Cache Hierarchy. - Craig R. Walters; Deanna Postles Dunn Berger; Robert J. Sonnelitter; Alper Buyuktosunoglu (HPCA, 2025)

The IBM Telum II Processor. - Christopher J. Berry; Michael J. Becht; Tim E. Bubb; Howard Haynie; Robert J. Sonnelitter; Katie Seggerman; Jonathan Hsieh; Edward Malley; Mike Cadigan; Susan M. Eickhoff; Matthias Klein; Craig R. Walters; et al. (IEEE Micro, 2025)