A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS. - Jiren Yuan; Crister Svensson (IEEE J. Solid State Circuits, 1994)

A 3-level asynchronous protocol for a differential two-wire communication link. - Crister Svensson; Jiren Yuan (IEEE J. Solid State Circuits, 1994)