A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. - Cristiano Santos; Gustavo Wilke; Cristiano Lazzari; Ricardo Reis 001; José Luís Almada Güntzel (SBCCI, 2003)

A New Macro-cell Generation Strategy for three metal layer CMOS Technologies. - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Almada Güntzel; Ricardo Augusto da Luz Reis (VLSI-SOC, 2003)

A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. - Cristiano Lazzari; Cristiano Viana Domingues; José Luís Güntzel; Ricardo Reis 001 (VLSI-SoC (Selected Papers), 2003)

Automatic Full-Custom Layout Generation of Static CMOS Circuits Targeting Delay and Power Reduction. - Cristiano Lazzari (IFIP Student Forum, 2004)

A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. - Fabricio B. Bastian; Cristiano Lazzari; José Luís Almada Güntzel; Ricardo Reis 001 (PATMOS, 2004)

On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. - Cristiano Lazzari; Lorena Anghel; Ricardo A. L. Reis (IOLTS, 2005)

A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. - Cristiano Lazzari; Lorena Anghel; Ricardo Reis 001 (VLSI-SoC, 2005)

A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits. - Cristiano Lazzari; Cristiano Santos; Ricardo Reis 001 (ICECS, 2006)

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (IOLTS, 2006)

Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies. - Lorena Anghel; Cristiano Lazzari; Michael Nicolaidis (LATW, 2006)

An Educational Tool for Design Automation of CMOS Cells. - Adriel Ziesemer; Cristiano Lazzari; Ricardo Reis 001 (MSE, 2007)

Efficient timing closure with a transistor level design flow. - Cristiano Lazzari; Cristiano Santos; Adriel Ziesemer; Lorena Anghel; Ricardo Reis 001 (VLSI-SoC, 2007)

Transistor level automatic layout generator for non-complementary CMOS cells. - Adriel Ziesemer; Cristiano Lazzari (VLSI-SoC, 2007)

A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. - Cristiano Lazzari; Ricardo A. L. Reis; Lorena Anghel (J. Electron. Test., 2007)

An automated design methodology for layout generation targeting power leakage minimization. - Cristiano Lazzari; Adriel Ziesemer; Ricardo Reis 001 (ICECS, 2009)

CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs. - Ricardo C. Goncalves da Silva; Cristiano Lazzari; Henri Boudinov; Luigi Carro (Microelectron. J., 2009)

A new quaternary FPGA based on a voltage-mode multi-valued circuit. - Cristiano Lazzari; Paulo F. Flores; José Monteiro 001; Luigi Carro (DATE, 2010)

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs. - Marcus Ritt; Carlos Arthur Lang Lisbôa; Luigi Carro; Cristiano Lazzari (FPL, 2010)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. - Sidinei Ghissoni; Eduardo Costa 001; Cristiano Lazzari; José Monteiro 001; Levent Aksoy; Ricardo Reis 001 (ICECS, 2010)

Voltage-mode quaternary FPGAs: An evaluation of interconnections. - Cristiano Lazzari; Paulo F. Flores; José Monteiro 001; Luigi Carro (ISCAS, 2010)

An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (PATMOS, 2010)

Efficient shift-adds design of digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ISCAS, 2011)

Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs. - Alexandre M. Amory; Cristiano Lazzari; Marcelo Lubaszewski; Fernando Gehm Moraes (SBCCI, 2011)

Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (J. Low Power Electron., 2011)

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms. - Alexandre M. Amory; Cristiano Lazzari; Marcelo Lubaszewski; Fernando Gehm Moraes (J. Parallel Distributed Comput., 2011)

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Integr., 2012)

Evaluating the scalability of test buses. - Alexandre M. Amory; Matheus T. Moreira; Ney Laert Vilar Calazans; Fernando Gehm Moraes; Cristiano Lazzari; Marcelo Soares Lubaszewski (ISSoC, 2013)

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)