Using Analog Scrambling Circuits for Automotive Sensor Integrity and Authenticity. - Cristiano Pegoraro Chenet; Alessandro Savino; Stefano Di Carlo (AQTR, 2022)

VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V Based Cloud Services. - Ramon Canal; Cristiano Pegoraro Chenet; Aggelos Arelakis; José-María Arnau; Josep Lluís Berral; Aaron Call; Stefano Di Carlo; Juan José Costa; Dimitris Gizopoulos; Vasileios Karakostas; Francesco Lubrano; Konstantinos Nikas; et al. (DSD, 2023)

Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective. - Marti Alonso; David Andreu 003; Ramon Canal; Stefano Di Carlo; Cristiano Pegoraro Chenet; Juanjo Costa; Andreu Girones; Dimitris Gizopoulos; Vasileios Karakostas; Beatriz Otero; George Papadimitriou 001; Eva Rodríguez; et al. (ETS, 2023)

A survey of hardware-based malware detection approach. - Cristiano Pegoraro Chenet; Alessandro Savino; Stefano Di Carlo (CoRR, 2023)

Special Session: Security and RAS in the Computing Continuum. - Marti Alonso; David Andreu 003; Ramon Canal; Stefano Di Carlo; Odysseas Chatzopoulos; Cristiano Pegoraro Chenet; Juanjo Costa; Andreu Girones; Dimitris Gizopoulos; George Papadimitriou 001; Enric Morancho; Beatriz Otero; et al. (DFT, 2024)

A Survey on Hardware-Based Malware Detection Approaches. - Cristiano Pegoraro Chenet; Alessandro Savino; Stefano Di Carlo (IEEE Access, 2024)

Hardware-based stack buffer overflow attack detection on RISC-V architectures. - Cristiano Pegoraro Chenet; Ziteng Zhang; Alessandro Savino; Stefano Di Carlo (CoRR, 2024)

Security and RAS in the Computing Continuum. - Marti Alonso; David Andreu 003; Ramon Canal; Stefano Di Carlo; Odysseas Chatzopoulos; Cristiano Pegoraro Chenet; Juanjo Costa; Andreu Girones; Dimitris Gizopoulos; George Papadimitriou 001; Enric Morancho; Beatriz Otero; et al. (CoRR, 2024)

Zero-Day Hardware-Supported Malware Detection of Stack Buffer Overflow Attacks: An Application Exploiting the CV32e40p RISC-V Core. - Cristiano Pegoraro Chenet; Alessandro Savino; Stefano Di Carlo (LATS, 2025)