Lagarto I - Una plataforma hardware/software de arquitectura de computadoras para la academia e investigación. - Cristóbal Ramírez; César Hernández; Carlos Rojas Morales; Gustavo Mondragón García; Luis A. Villa; Marco Antonio Ramírez (Res. Comput. Sci., 2017)

An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures. - Cristóbal Ramírez; César-Alejandro Hernández-Calderón; Oscar Palomar; Osman S. Unsal; Marco Antonio Ramírez; Adrián Cristal (ACM Trans. Archit. Code Optim., 2020)

Design and implementation of an out-of-order execution engine of floating-point arithmetic operations. - Cristóbal Ramírez Lazo (CoRR, 2021)

BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge. - Enrico Reggiani; Cristóbal Ramírez Lazo; Roger Figueras Bagué; Adrián Cristal; Mauro Olivieri; Osman Sabri Unsal (ASPLOS, 2022)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Adaptable Register File Organization for Vector Processors. - Cristóbal Ramírez Lazo; Enrico Reggiani; Carlos Rojas Morales; Roger Figueras Bagué; Luis A. Villa Vargas; Marco Antonio Ramírez Salinas; Mateo Valero Cortés; Osman Sabri Unsal; Adrián Cristal (HPCA, 2022)

Lagarto I-Una plataforma hardware/software de arquitectura de computadoras para la academia e investigación. - Cristóbal Ramírez Lazo; César-Alejandro Hernández-Calderón; Carlos Rojas Morales; Gustavo Mondragón García; Luis Alfonso Villa Vargas; Marco Antonio Ramírez Salinas (CoRR, 2022)

Adaptable register file organization for vector processors. - Cristóbal Ramírez (2022)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)