VLSI Design and Analysis of Multipliers for Low Power. - Pachara V. Rao; Cyril Prasanna Raj; S. Ravi 001 (IIH-MSP, 2009)

Design and Verification of Cache Memory Decoder for High Speed Multicore Processor. - A. Ravi Kumar; Cyril Prasanna Raj; G. M. Sree Rama Reddy (ICETET, 2010)

VLSI Architecuture for Neural Network Based Image Compression. - K. V. Venkata Ramanaiah; Cyril Prasanna Raj (ICETET, 2010)

Design and VLSI Implementation of Interpolators/Decimators for DUC/DDC. - Y. N. Santhosh; Namita Palacha; Cyril Prasanna Raj (ICETET, 2010)

Analysis of Wavelet for 3D-DWT Volumetric Image Compression. - B. M. Sunil; Cyril Prasanna Raj (ICETET, 2010)

FPGA Based Reconfigurable 200 MHz Transmitter and Receiver Front End for MIMO-OFDM. - M. B. Veena; Cyril Prasanna Raj; M. N. Shanmukha Swamy (ICETET, 2010)

High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA. - S. S. Divakara; Sudarshan Patilkulkarni; Cyril Prasanna Raj (Int. J. Wavelets Multiresolution Inf. Process., 2017)

High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT. - S. S. Divakara; Sudarshan Patilkulkarni; Cyril Prasanna Raj (Int. J. Image Graph., 2018)

Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic. - S. S. Divakara; Sudarshan Patilkulkarni; Cyril Prasanna Raj (Int. J. Image Graph., 2020)