Application of a design space exploration tool to enhance interleaver generation. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (EUSIPCO, 2007)

A design methodology for space-time adapter. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (ACM Great Lakes Symposium on VLSI, 2007)

A design flow dedicated to multi-mode architectures for DSP applications. - Cyrille Chavet; Caaliph Andriamisaina; Philippe Coussy; Emmanuel Casseau; Emmanuel Juin; Pascal Urard; Eric Martin 001 (ICCAD, 2007)

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (ISCAS, 2007)

Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (CoRR, 2007)

Synthèse automatique d'interfaces de communication matérielles pour la conception d'applications du domaine du traitement du signal. (Automatic synthesis of hardware communication interfaces for Data Signal Processing applications). - Cyrille Chavet (2007)

Static Address Generation Easing: a design methodology for parallel interleaver architectures. - Cyrille Chavet; Philippe Coussy; Pascal Urard; Eric Martin 001 (ICASSP, 2010)

Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ICECS, 2010)

A memory mapping approach for parallel interleaver design with multiples read and write accesses. - Cyrille Chavet; Philippe Coussy (ISCAS, 2010)

High-Level Synthesis for Designing Multimode Architectures. - Caaliph Andriamisaina; Philippe Coussy; Emmanuel Casseau; Cyrille Chavet (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

High-Level Synthesis: On the path to ESL design. - Philippe Coussy; Dominique Heller; Cyrille Chavet (ASICON, 2011)

A methodology based on Transportation problem modeling for designing parallel interleaver architectures. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ICASSP, 2011)

An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. - Awais Sani; Philippe Coussy; Cyrille Chavet; Eric Martin 001 (ISCAS, 2011)

OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. - Paolo Burgio; Andrea Marongiu; Dominique Heller; Cyrille Chavet; Philippe Coussy; Luca Benini (DSD, 2012)

A design approach dedicated to network-based and conflict-free parallel interleavers. - Aroua Briki; Cyrille Chavet; Philippe Coussy; Eric Martin 001 (ACM Great Lakes Symposium on VLSI, 2012)

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. - Oscar Sanchez; Michel Jézéquel; Saeed-ur Rehman; Awais Sani; Cyrille Chavet; Philippe Coussy; Christophe Jégo (SiPS, 2012)

Dynamic branch prediction for high-level synthesis. - Vianney Lapotre; Philippe Coussy; Cyrille Chavet; Hugues Wouafo; Robin Danilo (FPL, 2013)

A memory mapping approach for network and controller optimization in parallel interleaver architectures. - Aroua Briki; Cyrille Chavet; Philippe Coussy (ACM Great Lakes Symposium on VLSI, 2013)

On-chip implementation of memory mapping algorithm to support flexible decoder architecture. - Saeed-ur Rehman; Awais Sani; Philippe Coussy; Cyrille Chavet (ICASSP, 2013)

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller. - Aroua Briki; Cyrille Chavet; Philippe Coussy (SiPS, 2013)

Introduction de la prédiction de branchement dans la synthèse de haut niveau. - Vianney Lapotre; Philippe Coussy; Cyrille Chavet (Tech. Sci. Informatiques, 2013)

A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. - Awais Hussain Sani; Philippe Coussy; Cyrille Chavet (IEEE Trans. Signal Process., 2013)

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures. - Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy (ACM Great Lakes Symposium on VLSI, 2014)

Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. - Saeed-ur Rehman; Awais Sani; Cyrille Chavet; Philippe Coussy (ICASSP, 2014)

A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. - Mickael Lanoe; Matteo Bordin; Dominique Heller; Philippe Coussy; Cyrille Chavet (ICECS, 2014)

In-place memory mapping approach for optimized parallel hardware interleaver architectures. - Saeed Ur Reehman; Cyrille Chavet; Philippe Coussy; Awais Sani (DATE, 2015)

Improving storage of patterns in recurrent neural networks: Clone-based model and architecture. - Hugues Wouafo; Cyrille Chavet; Philippe Coussy (ISCAS, 2015)

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories. - Philippe Coussy; Cyrille Chavet; Hugues Nono Wouafo; Laura Conde-Canencia (ACM J. Emerg. Technol. Comput. Syst., 2015)

Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection. - Robin Danilo; Hugues Nono Wouafo; Cyrille Chavet; Vincent Gripon; Laura Conde-Canencia; Philippe Coussy (DASIP, 2016)

A dynamically reconfigurable ECC decoder architecture. - Awais Sani; Philippe Coussy; Cyrille Chavet (DATE, 2016)

Efficient scalable hardware architecture for highly performant encoded neural networks. - Hugues Wouafo; Cyrille Chavet; Philippe Coussy; Robin Danilo (SiPS, 2017)

Solving Memory Access Conflicts in LTE-4G Standard. - Cyrille Chavet; Fabrice Lozachmeur; T. Barguil; A. S. Hussein; Philippe Coussy (ICASSP, 2019)

Clone-Based Encoded Neural Networks to Design Efficient Associative Memories. - Hugues Wouafo; Cyrille Chavet; Philippe Coussy (IEEE Trans. Neural Networks Learn. Syst., 2019)

Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation. - Ghita Harcha; Vianney Lapôtre; Cyrille Chavet; Philippe Coussy (ISCAS, 2020)

Fully Parallel Circular-Shift Rotation Network for Communication Standards. - Hassan Harb; Cyrille Chavet (IEEE Trans. Circuits Syst., 2020)

Extended RISC-V hardware architecture for future digital communication systems. - Maël Tourres; Cyrille Chavet; Bertrand Le Gal; Jérémie Crenne; Philippe Coussy (5GWF, 2021)

Back-to-Back Butterfly Network, an Adaptive Permutation Network for New Communication Standards. - Hassan Harb; Cyrille Chavet (J. Signal Process. Syst., 2021)

WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU). - Klaus Hofmann; Ferdinand Keil; David Riehl; Alicja Michalowska-Forsyth; Nikolaus Czepl; Sarah Woywod; Dominik Zupan; Mario R. Casu; Carlo Ricciardi; Massimo Violante; Mariagrazia Graziano; Yuri Ardesi; et al. (FIE, 2024)

Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors. - Maël Tourres; Cyrille Chavet; Bertrand Le Gal; Philippe Coussy (IEEE Access, 2025)