Parity prediction synthesis for nano-electronic gate designs. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (ITC, 2010)

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

A pseudo-dynamic comparator for error detection in fault tolerant architectures. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Michael E. Imhof; Hans-Joachim Wunderlich (VTS, 2012)

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (J. Electron. Test., 2014)