Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; K. Banerjee; H. Puliyalil; Shreya Kundu; M. Pak; et al. (ICICDT, 2022)

Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; S. Sutar; L. Magnarin; Umberto Celano; H. Puliyalil; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Integration of a Stacked Contact MOL for Monolithic CFET. - Victor Vega-Gonzalez; D. Radisic; Bt Chan; S. Choudhury; S. Wang; A. Mingardi; Q. Toan Le; H. Decoster; Yusuke Oniki; P. Puttarame; Kevin Vandersmissen; J. P. Soulie; et al. (VLSI Technology and Circuits, 2023)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)