A clock power model to evaluate impact of architectural and technology optimizations. - D. E. Duarte; Narayanan Vijaykrishnan; Mary Jane Irwin (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Characterization and modeling of run-time techniques for leakage power reduction. - Yuh-Fang Tsai; D. E. Duarte; Narayanan Vijaykrishnan; Mary Jane Irwin (IEEE Trans. Very Large Scale Integr. Syst., 2004)