BIST Based Performance Evaluation of Field Programmable Analog Arrays. - Savita Charhate; D. K. Mishra (ICETET, 2008)

A two stage and three stage CMOS OPAMP with fast settling, high DC gain and low power designed in 180nm technology. - Anshu Gupta; D. K. Mishra; Rajesh Khatri; U. B. S. Chandrawat; Preet Jain (CISIM, 2010)

A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions. - Dinesh Kushwaha; D. K. Mishra (ICIIS, 2016)

A Single-Ended Read Decoupled 9T SRAM Cell for Low Power Applications. - Shivram Mansore; Radheshyam Gamad; D. K. Mishra (iNIS, 2017)

A 32 nm Read Disturb-free 11T SRAM Cell with Improved Write Ability. - S. R. Mansore; R. S. Gamad 001; D. K. Mishra (J. Circuits Syst. Comput., 2020)

Precision measurement of ADC parameters with cumulative histogram technique using Gaussian noise. - Bhawana Garg; D. K. Mishra (Microelectron. J., 2020)