Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. - Shusuke Yoshimoto; Takuro Amashita; D. Kozuwa; Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2011)