VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. - D. M. H. Walker; Stephen W. Director (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

DVLASIC: catastrophic fault yield simulation in a distributed processing environment. - Duncan M. Hank Walker; D. S. Nydick (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. - D. M. H. Walker; Chris S. Kellen; Andrzej J. Strojwas (DAC, 1991)

Test quality and yield analysis using the DEFAM defect to fault mapper. - Dinesh D. Gaitonde; Duncan M. Hank Walker (ICCAD, 1993)

Estimation of reject ratio in testing of combinatorial circuits. - Dinesh D. Gaitonde; Jitendra Khare; D. M. H. Walker; Wojciech P. Maly (VTS, 1993)

The CDB/HCDB semiconductor wafer representation server. - D. M. H. Walker; Chris S. Kellen; David M. Svoboda; Andrzej J. Strojwas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Semiconductor wafer representation for TCAD. - Martin D. Giles; Duane S. Boning; Goodwin R. Chin; Walter C. Dietrich Jr.; Michael S. Karasick; Mark E. Law; Purnendu K. Mozumder; Lee R. Nackman; V. T. Rajan; Duncan M. Hank Walker; Robert H. Wang; Alexander S. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Accurate yield estimation of circuits with redundancy. - Dinesh D. Gaitonde; D. M. H. Walker; Wojciech Maly (DFT, 1995)

Yiel Learning via Functional Test Data. - Young-Jun Kwon; D. M. H. Walker (ITC, 1995)

IC Performance Prediction System. - V. Ramakrishnan; D. M. H. Walker (ITC, 1995)

Fatal Fault Probability Prediction for Array Based Designs. - Dinesh D. Gaitonde; Wojciech Maly; D. M. H. Walker (DFT, 1996)

Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. - Yuyun Liao; D. M. H. Walker (ITC, 1996)

Test Generation for Global Delay Faults. - G. M. Luong; D. M. H. Walker (ITC, 1996)

Improvement of SRAM-based failure analysis using calibrated Iddq testing. - Hari Balachandran; D. M. H. Walker (VTS, 1996)

Optimal voltage testing for physically-based faults. - Yuyun Liao; D. M. H. Walker (VTS, 1996)

Accurate Fault Modeling and Fault Simulation of Resistive Bridges. - Vijay R. Sar-Dessai; D. M. H. Walker (DFT, 1998)

Bridging Fault Detection in FPGA Interconnects Using IDDQ. - Lan Zhao 002; D. M. H. Walker; Fabrizio Lombardi (FPGA, 1998)

Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. - Lan Zhao 002; D. M. H. Walker; Fabrizio Lombardi (ITC, 1998)

IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. - Lan Zhao 002; D. M. H. Walker; Fabrizio Lombardi (IEEE Trans. Computers, 1998)

IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. - Lan Zhao 002; D. M. H. Walker; Fabrizio Lombardi (Asian Test Symposium, 1999)

Resistive bridge fault modeling, simulation and test generation. - Vijay R. Sar-Dessai; D. M. H. Walker (ITC, 1999)

Design for Yield and Reliability is MORE Important Than DFT. - D. M. H. Walker (ITC, 1999)

Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. - Debashis Nayak; D. M. H. Walker (VTS, 1999)

Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. - Zoran Stanojevic; Hari Balachandran; D. M. H. Walker; Fred Lakbani; Jayashree Saxena; Kenneth M. Butler (ITC, 2000)

Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. - Byungwoo Choi; D. M. H. Walker (VTS, 2000)

PROBE: A PPSFP Simulator for Resistive Bridging Faults. - Chul Young Lee; D. M. H. Walker (VTS, 2000)

An efficient solution to the storage correspondence problem for large sequential circuits. - Wanlin Cao; D. M. H. Walker; Rajarshi Mukherjee (ASP-DAC, 2001)

A practical built-in current sensor for I_DDQ testing. - Hoki Kim; D. M. H. Walker; David Colby (ITC, 2001)

Improved wafer-level spatial analysis for I_DDQ limit setting. - Sagar S. Sabade; D. M. H. Walker (ITC, 2001)

FedEx - a fast bridging fault extractor. - Zoran Stanojevic; D. M. H. Walker (ITC, 2001)

Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. - Sagar S. Sabade; D. M. H. Walker (DFT, 2002)

Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. - Sagar S. Sabade; D. M. H. Walker (ASP-DAC/VLSI Design, 2002)

Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. - Sagar S. Sabade; D. M. H. Walker (VTS, 2002)

IDDQ Test: Will It Survive the DSM Challenge? - Sagar S. Sabade; D. M. H. Walker (IEEE Des. Test Comput., 2002)

Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. - Abhijit Prasad; D. M. H. Walker (DFT, 2003)

CodSim – A Combined Delay Fault Simulator. - Wangqi Qiu; Xiang Lu; Zhuo Li 001; D. M. H. Walker; Weiping Shi (DFT, 2003)

CROWNE: Current Ratio Outliers with Neighbor Estimator. - Sagar S. Sabade; D. M. H. Walker (DFT, 2003)

An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. - Wangqi Qiu; D. M. H. Walker (ITC, 2003)

Testing the Path Delay Faults of ISCAS85 Circuit c6288. - Wangqi Qiu; D. M. H. Walker (MTV, 2003)

Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. - Sagar S. Sabade; D. M. H. Walker (VLSI Design, 2003)

A Circuit Level Fault Model for Resistive Opens and Bridges. - Zhuo Li 001; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (VTS, 2003)

Use of Multiple IDDQ Test Metrics for Outlier Identification. - Sagar S. Sabade; D. M. H. Walker (VTS, 2003)

A circuit level fault model for resistive bridges. - Zhuo Li 001; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (ACM Trans. Design Autom. Electr. Syst., 2003)

PARADE: PARAmetric Delay Evaluation under Process Variation. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (ISQED, 2004)

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. - Wangqi Qiu; Jing Wang 006; D. M. H. Walker; Divya Reddy; Zhuo Li 001; Weiping Shi; Hari Balachandran (ITC, 2004)

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (MTV, 2004)

Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. - Sagar S. Sabade; D. M. H. Walker (VLSI Design, 2004)

A Statistical Fault Coverage Metric for Realistic Path Delay Faults. - Wangqi Qiu; Xiang Lu; Jing Wang 006; Zhuo Li 001; D. M. H. Walker; Weiping Shi (VTS, 2004)

On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. - Sagar S. Sabade; D. M. H. Walker (VTS, 2004)

IDDQ data analysis using neighbor current ratios. - Sagar S. Sabade; D. M. H. Walker (J. Syst. Archit., 2004)

IDDX-based test methods: A survey. - Sagar S. Sabade; D. M. H. Walker (ACM Trans. Design Autom. Electr. Syst., 2004)

A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. - Lei Wu 009; D. M. H. Walker (DFT, 2005)

A vector-based approach for power supply noise analysis in test compaction. - Jing Wang 006; Ziding Yue; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (ITC, 2005)

IDDQ test using built-in current sensing of supply line voltage drop. - Bin Xue; D. M. H. Walker (ITC, 2005)

Reliable energy efficient routing in wireless sensor networks. - Eunjae Jung; Duncan M. Hank Walker (MASS, 2005)

Is IDDQ Test of Microprocessors Feasible? - Bin Xue; D. M. H. Walker (MTV, 2005)

Static Compaction of Delay Tests Considering Power Supply Noise. - Jing Wang 006; Xiang Lu; Wangqi Qiu; Ziding Yue; Steve Fancler; Weiping Shi; D. M. H. Walker (VTS, 2005)

IC Outlier Identification Using Multiple Test Metrics. - Sagar S. Sabade; Duncan M. Hank Walker (IEEE Des. Test Comput., 2005)

Longest-path selection for delay test under process variation. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Comparison of Delay Tests on Silicon. - Wangqi Qiu; D. M. H. Walker; Neil Simpson; Divya Reddy; Anthony Moore (ITC, 2006)

Power Supply Noise in Delay Testing. - Jing Wang 006; D. M. H. Walker; Ananta K. Majhi; Bram Kruseman; Guido Gronthoud; Luis Elvira Villagra; Paul van de Wiel; Stefan Eichenberger (ITC, 2006)

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. - Hyun Sung Kim; D. M. H. Walker (MTV, 2006)

Estimation of fault-free leakage current using wafer-level spatial information. - Sagar S. Sabade; D. M. H. Walker (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Modeling Power Supply Noise in Delay Testing. - Jing Wang 006; Duncan M. Hank Walker; Xiang Lu; Ananta K. Majhi; Bram Kruseman; Guido Gronthoud; Luis Elvira Villagra; Paul J. A. M. van de Wiel; Stefan Eichenberger (IEEE Des. Test Comput., 2007)

Dynamic Compaction for High Quality Delay Test. - Zheng Wang; D. M. H. Walker (VTS, 2008)

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. - Kanupriya Gulati; Nikhil Jayakumar; Sunil P. Khatri; D. M. H. Walker (Integr., 2008)

Challenges in Delay Testing of Integrated Circuits. - D. M. H. Walker (DFT, 2009)

Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. - Zheng Wang; Duncan M. Hank Walker (VTS, 2009)

Levelized low cost delay test compaction considering IR-drop induced power supply noise. - Zhongwei Jiang; Zheng Wang; Jing Wang 006; D. M. H. Walker (VTS, 2011)

Maximizing crosstalk-induced slowdown during path delay test. - Dibakar Gope; D. M. H. Walker (ICCD, 2012)

Mixed structural-functional path delay test generation and compaction. - Kun Bian; D. M. H. Walker; Sunil P. Khatri; Shayak Lahiri (DFTS, 2013)

Power supply noise control in pseudo functional test. - Tengteng Zhang; Duncan M. Hank Walker (VTS, 2013)

K Longest Paths. - Duncan M. Hank Walker (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Delay Test of Embedded Memories. - Yukun Gao; Tengteng Zhang; Swati Chakraborty; D. M. H. Walker (NATW, 2014)

Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. - Tengteng Zhang; Yukun Gao; D. M. H. Walker (NATW, 2014)

Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. - Kun Bian; D. M. H. Walker; Sunil P. Khatri (VLSID, 2014)

Improved power supply noise control for pseudo functional test. - Tengteng Zhang; Duncan M. Hank Walker (VTS, 2014)

Impact of test compression on power supply noise control. - Tengteng Zhang; D. M. H. Walker (DFTS, 2015)

Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. - Avijit Chakraborty; D. M. H. Walker (ACM Great Lakes Symposium on VLSI, 2015)

At-Speed Path Delay Test. - Swati Chakraborty; Duncan M. Hank Walker (NATW, 2015)

Pseudo Functional Path Delay Test through Embedded Memories. - Yukun Gao; Tengteng Zhang; Punj Pokharel; Swati Chakraborty; D. M. H. Walker (J. Electron. Test., 2015)

Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. - Tengteng Zhang; Yukun Gao; D. M. H. Walker (J. Electron. Test., 2015)

Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. - Prasenjit Biswas; D. M. H. Walker (VLSID, 2017)

Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. - Avijit Chakraborty; D. M. H. Walker (DFT, 2020)

Topological Heuristics for Scan Test Overhead Reduction. - Avijit Chakraborty; Duncan M. Hank Walker (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)