Logic circuit design with gates, LUTs and MUXs oriented to mask faults. - Anzhela Yu. Matrosova; Sergey Ostanin; D. Tretyakov; Natalia Butorina (EWDTS, 2017)

Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults. - Sergey Ostanin; Valentina Andreeva; Natalia Butorina; D. Tretyakov (EWDTS, 2018)