Design and VLSI implementation of a novel concurrent 16-bit multiplier-accumulator for DSP applications. - D. V. Poornaiah; R. Haribabu; M. Omair Ahmad (ICASSP (1), 1993)

Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. - D. V. Poornaiah; P. V. Ananda Mohan (VLSI Design, 1995)

A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applications. - D. V. Poornaiah; P. V. Ananda Mohan (VLSI Design, 1996)