A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. - Chang-Hyun Kim; Jung-Hwa Lee; J. B. Lee; Beomsup Kim; C. S. Park; Sang-Bo Lee; S. Y. Lee; C. W. Park; J. G. Roh; Hyoung Sik Nam; D. Y. Kim; D. Y. Lee; et al. (IEEE J. Solid State Circuits, 1998)

New colonoscopy simulator with improved haptic fidelity. - S. Y. Yi; H. S. Woo; W. J. Ahn; J. Y. Kwon; D. Y. Lee (Adv. Robotics, 2006)

A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications. - Wei-Chih Chien; E. K. Lai; L. Buzi; C. W. Cheng; C. W. Yeh; A. Ray; Lynne M. Gignac; N. Gong; Huai-Yu Cheng; Alexander Grun; D. Y. Lee; W. Kim; et al. (IMW, 2023)