33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. - Weier Wan; Rajkumar Kubendran; Sukru Burc Eryilmaz; Wenqiang Zhang; Yan Liao; Dabin Wu; Stephen R. Deiss; Bin Gao 006; Priyanka Raina; Siddharth Joshi 001; Huaqiang Wu; Gert Cauwenberghs; et al. (ISSCC, 2020)

HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU. - Yanhai Jiang; Bin Gao 006; Jianshi Tang; Dabin Wu; Hu He 001; He Qian; Huaqiang Wu (ICTA, 2021)

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (CoRR, 2021)

A compute-in-memory chip based on resistive random-access memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (Nat., 2022)

A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit. - Hanwen Gong; Hu He 001; Bin Gao 006; Jianshi Tang; Jian Yu; Dabin Wu; Junren Chen; Qingtian Zhang; Xing Mou; He Qian; Huaqiang Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration. - Hanwen Gong; Hu He 001; Liyang Pan; Bin Gao 006; Jianshi Tang; Sining Pan; Jianing Li; Peng Yao; Dabin Wu; He Qian; Huaqiang Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)