Brain Storm Optimization Algorithm with Modified Step-Size and Individual Generation. - Dadian Zhou; Yuhui Shi 001; Shi Cheng (ICSI (1), 2012)

A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. - Dadian Zhou; Claudio Talarico; José Silva-Martínez (SoCC, 2016)

A 13bit 200MS/S pipeline ADC with current-mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; José Silva-Martínez (ISCAS, 2017)

A 200MSPS time-interleaved 12-bit ADC system with digital calibration. - Aditya Bommireddipalli; Dadian Zhou; Claudio Talarico; José Silva-Martínez; Aydin I. Karsilayan (MWSCAS, 2017)

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. - Carlos Briseno-Vidrios; Dadian Zhou; Suraj Prakash; Qiyuan Liu 001; Alexander Edward; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE J. Solid State Circuits, 2018)

A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. - Qiyuan Liu 001; Alexander Edward; Dadian Zhou; José Silva-Martínez (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration. - Dadian Zhou; Carlos Briseno-Vidrios; Junning Jiang; Chulhyun Park; Qiyuan Liu 001; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator. - Dadian Zhou; Junning Jiang; Qiyuan Liu 001; Eric G. Soenen; Martin Kinyua; José Silva-Martínez (IEEE J. Solid State Circuits, 2020)

A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier. - Chulhyun Park; Tao Chen 006; Kyoohyun Noh; Dadian Zhou; Suraj Prakash; Mohammadhossein Naderi Alizadeh; Aydin I. Karsilayan; Degang Chen 001; Randall L. Geiger; José Silva-Martínez (IEEE Trans. Circuits Syst., 2020)

A Low-Cost On-Chip Built-In Self-Test Solution for ADC Linearity Test. - Tao Chen 006; Chulhyun Park; Hao Meng; Dadian Zhou; José Silva-Martínez; Randall L. Geiger; Degang Chen 001 (IEEE Trans. Instrum. Meas., 2020)

Recent Advances on Linear Low-Dropout Regulators. - José Silva-Martínez; Xiaosen Liu; Dadian Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Look-Up Table-Based Digital Calibration for the Correction of Pipeline Analog-to-Digital Converter Non-Idealities. - Shangfeng Qiu; Dadian Zhou; Martin Kinyua; Jose Silva-Martinez (IEEE Access, 2024)

Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs. - Amr Walid; Dadian Zhou; Jose Silva-Martinez (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)