An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. - Seung-Jun Bae; Young-Soo Sohn; Kwang-Il Park; Kyoung-Ho Kim; Dae-Hyun Chung; Jingook Kim; Si-Hong Kim; Min-Sang Park; Jae-Hyung Lee; Sam-Young Bang; Ho-Kyung Lee; In-Soo Park; et al. (ISSCC, 2008)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates. - Prashant J. Nair; Dae-Hyun Kim 003; Moinuddin K. Qureshi (ISCA, 2013)

AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems. - Moinuddin K. Qureshi; Dae-Hyun Kim 003; Samira Manabi Khan; Prashant J. Nair; Onur Mutlu (DSN, 2015)

Architectural Support for Mitigating Row Hammering in DRAM Memories. - Dae-Hyun Kim 003; Prashant J. Nair; Moinuddin K. Qureshi (IEEE Comput. Archit. Lett., 2015)

The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system. - Soonyoung Cha; Dae Hyun Kim 003; Taizhi Liu; Linda S. Milor (Microelectron. Reliab., 2015)

AVERT: An elaborate model for simulating variable retention time in DRAMs. - Dae Hyun Kim 003; Soonyoung Cha; Linda S. Milor (Microelectron. Reliab., 2015)

Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. - Dae Hyun Kim 003; Soonyoung Cha; Linda S. Milor (Microelectron. Reliab., 2015)

ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. - Dae Hyun Kim 003; Linda S. Milor (VTS, 2016)

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array. - Woongrae Kim; Chang-Chih Chen; Dae Hyun Kim 003; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes. - Dae-Hyun Kim 003; Linda Milor (VTS, 2017)

Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test. - Dae-Hyun Kim 003; Linda Milor (Microelectron. Reliab., 2017)

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits. - Kexin Yang 001; Taizhi Liu; Rui Zhang 048; Dae Hyun Kim 003; Linda Milor (Microelectron. Reliab., 2017)

An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems. - Dae-Hyun Kim 003; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Design methodologies for scalable and reliable memory systems. - Dae-Hyun Kim 003 (2017)

Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks. - Amirali Boroumand; Saugata Ghose; Youngsok Kim; Rachata Ausavarungnirun; Eric Shiu; Rahul Thakur; Daehyun Kim 003; Aki Kuusela; Allan Knies; Parthasarathy Ranganathan; Onur Mutlu (ASPLOS, 2018)

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology. - Kexin Yang 001; Rui Zhang 048; Taizhi Liu; Dae Hyun Kim 003; Linda Milor (DCIS, 2018)

μLayer: Low Latency On-Device Inference Using Cooperative Single-Layer Acceleration and Processor-Friendly Quantization. - Youngsok Kim; Joonsung Kim; Dongju Chae; Daehyun Kim 003; Jangwoo Kim (EuroSys, 2019)

Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. - Dae-Hyun Kim 003; Shu-Han Hsu; Linda Milor (IEEE Trans. Very Large Scale Integr. Syst., 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. - Yong-Hun Kim; Hyung-Jin Kim; Jaemin Choi; Min-Su Ahn; Dongkeon Lee; Seung-Hyun Cho; Dong-Yeon Park; Young-Jae Park; Min-Soo Jang; Yong-Jun Kim; Jinyong Choi; Sung-Woo Yoon; et al. (ISSCC, 2021)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. - Dae-Hyun Kim 003; Byungkyu Song; Hyun-A. Ahn; Woongjoon Ko; Sung-Geun Do; Seokjin Cho; Kihan Kim; Seung-Hoon Oh; Hye-Yoon Joo; Geuntae Park; Jin-Hun Jang; Yong-Hun Kim; et al. (ISSCC, 2022)