Bus-aware microarchitectural floorplanning. - Dae Hyun Kim 004; Sung Kyu Lim (ASP-DAC, 2008)

Global bus route optimization with application to microarchitectural design exploration. - Dae Hyun Kim 004; Sung Kyu Lim (ICCD, 2008)

A study of Through-Silicon-Via impact on the 3D stacked IC layout. - Dae Hyun Kim 004; Krit Athikulwongse; Sung Kyu Lim (ICCAD, 2009)

Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. - Dae Hyun Kim 004; Saibal Mukhopadhyay; Sung Kyu Lim (SLIP, 2009)

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. - Michael B. Healy; Krit Athikulwongse; Rohan Goel; Mohammad M. Hossain; Dae Hyun Kim 004; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Moongon Jung; Brian Ouellette; Mohit Pathak; et al. (CICC, 2010)

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. - Minki Cho; Chang Liu 034; Dae Hyun Kim 004; Sung Kyu Lim; Saibal Mukhopadhyay (ICCAD, 2010)

Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs. - Daehyun Kim 004; Sung Kyu Lim (SLIP, 2010)

Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. - Muhammad Bashir; Linda S. Milor; Dae Hyun Kim 004; Sung Kyu Lim (Microelectron. Reliab., 2010)

TSV density-driven global placement for 3D stacked ICs. - Dae Hyun Kim 004; Rasit Onur Topaloglu; Sung Kyu Lim (ISOCC, 2011)

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. - Taigon Song; Chang Liu 034; Dae Hyun Kim 004; Sung Kyu Lim; Jonghyun Cho; Joohee Kim; Junso Pak; Seungyoung Ahn; Joungho Kim; Kihyun Yoon (ISQED, 2011)

Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designs. - Daehyun Kim 004; Suyoun Kim; Sung Kyu Lim (SLIP, 2011)

Impact of irregular geometries on low-k dielectric breakdown. - Muhammad Bashir; Linda Milor; Dae Hyun Kim 004; Sung Kyu Lim (Microelectron. Reliab., 2011)

Block-level 3D IC design with through-silicon-via planning. - Dae Hyun Kim 004; Rasit Onur Topaloglu; Sung Kyu Lim (ASP-DAC, 2012)

Design quality tradeoff studies for 3D ICs built with nano-scale TSVs and devices. - Kaiyuan Yang 001; Dae Hyun Kim 004; Sung Kyu Lim (ISQED, 2012)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices. - Dae Hyun Kim 004; Sung Kyu Lim (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Backend dielectric reliability simulator for microprocessor system. - Chang-Chih Chen; Fahad Ahmed; Dae Hyun Kim 004; Sung Kyu Lim; Linda Milor (Microelectron. Reliab., 2012)

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. - Krit Athikulwongse; Dae Hyun Kim 004; Moongon Jung; Sung Kyu Lim (ASP-DAC, 2013)

Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. - Dae Hyun Kim 004; Krit Athikulwongse; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Simulation of system backend dielectric reliability. - Chang-Chih Chen; Muhammad Bashir; Linda S. Milor; Daehyun Kim 004; Sung Kyu Lim (Microelectron. J., 2014)

TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs. - Daehyun Kim 004; Saibal Mukhopadhyay; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Backend Dielectric Reliability Full Chip Simulator. - Muhammad Muqarrab Bashir; Chang-Chih Chen; Linda Milor; Dae Hyun Kim 004; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures. - Sourav Das 002; Dongjin Lee; Dae Hyun Kim 004; Partha Pratim Pande (ACM Great Lakes Symposium on VLSI, 2015)

Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach. - Sourav Das 002; Janardhan Rao Doppa; Daehyun Kim 004; Partha Pratim Pande; Krishnendu Chakrabarty (ICCAD, 2015)

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools. - Dae Hyun Kim 004; Sung Kyu Lim (IEEE Des. Test, 2015)

Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities. - Dae Hyun Kim 004; Sung Kyu Lim (IEEE Des. Test, 2015)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)

Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs. - Sheng-En David Lin; Partha Pratim Pande; Dae Hyun Kim 004 (ISQED, 2016)

Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2. - Daehyun Kim 004; Sung Kyu Lim (IEEE Des. Test, 2016)

A legalization algorithm for multi-tier gate-level monolithic three-dimensional integrated circuits. - Yiting Chen; Dae Hyun Kim 004 (ISQED, 2017)

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid. - Sheng-En David Lin; Dae Hyun Kim 004 (ISPD, 2018)

Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach. - Dongjin Lee; Sourav Das 002; Dae Hyun Kim 004; Janardhan Rao Doppa; Partha Pratim Pande (ACM J. Emerg. Technol. Comput. Syst., 2018)

Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits. - Inki Hong; Dae Hyun Kim 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs. - Sheng-En David Lin; Dae Hyun Kim 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding. - Jihee Seo; Dae Hyun Kim 004 (ARITH, 2019)

Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers. - Jihee Seo; Dae Hyun Kim 004 (DATE, 2019)

Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing. - Sheng-En David Lin; Dae Hyun Kim 004 (ISPD, 2019)

A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design. - Shantonu Das; Dae Hyun Kim 004 (ISQED, 2019)

Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits. - Sheng-En David Lin; Dae Hyun Kim 004 (ISQED, 2019)

Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures. - Shouvik Musavvir; Anwesha Chatterjee; Ryan Gary Kim; Dae Hyun Kim 004; Partha Pratim Pande (CoRR, 2019)

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs. - Sheng-En David Lin; Dae Hyun Kim 004 (IEEE Trans. Emerg. Top. Comput., 2019)

Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips. - Shouvik Musavvir; Anwesha Chatterjee; Ryan Gary Kim; Dae Hyun Kim 004; Janardhan Rao Doppa; Partha Pratim Pande (DATE, 2020)

RTL-to-GDS Design Tools for Monolithic 3D ICs. - Jinwoo Kim; Gauthaman Murali; Pruek Vanna-Iampikul; Edward Lee; Daehyun Kim 004; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty; Saibal Mukhopadhyay; Sung Kyu Lim (ICCAD, 2020)

NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization. - Monzurul Islam Dewan; Dae Hyun Kim 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design. - Sheng-En David Lin; Dae Hyun Kim 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration. - Shouvik Musavvir; Anwesha Chatterjee; Ryan Gary Kim; Dae Hyun Kim 004; Partha Pratim Pande (IEEE Trans. Very Large Scale Integr. Syst., 2020)

HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration. - Aqeeb Iqbal Arka; Biresh Kumar Joardar; Ryan Gary Kim; Dae Hyun Kim 004; Janardhan Rao Doppa; Partha Pratim Pande (ACM Trans. Design Autom. Electr. Syst., 2021)

Bayesian Optimization over Permutation Spaces. - Aryan Deshwal; Syrine Belakaria; Janardhan Rao Doppa; Dae Hyun Kim 004 (AAAI, 2022)

A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process. - Edward Lee; Daehyun Kim 004; Jinwoo Kim; Sung Kyu Lim; Saibal Mukhopadhyay (ACM J. Emerg. Technol. Comput. Syst., 2022)

Design Automation Algorithms for the NP-Separate VLSI Design Methodology. - Monzurul Islam Dewan; Dae Hyun Kim 004 (ACM Trans. Design Autom. Electr. Syst., 2022)

Dual-Purpose Hardware Algorithms and Architectures - Part 2: Integer Division. - Jihee Seo; Dae-Hyun Kim 004 (ARITH, 2023)

Dual-Purpose Hardware Algorithms and Architectures - Part 1: Floating-Point Division. - Jihee Seo; Dae-Hyun Kim 004 (ARITH, 2023)

Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing. - Monzurul Islam Dewan; Sheng-En David Lin; Dae Hyun Kim 004 (ACM Trans. Design Autom. Electr. Syst., 2024)