CMOS RF transmitter with integrated power amplifier utilizing digital equalization. - Dae Hyun Kwon; Hao Li 001; Yuchun Chang; Richard Tseng; Yun Chiu (CICC, 2009)

A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation. - Hao Li 001; Dae Hyun Kwon; Deming Chen; Yun Chiu (IEEE J. Sel. Top. Signal Process., 2009)

Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier. - Dae Hyun Kwon; Hao Li 001; Yuchun Chang; Richard Tseng; Yun Chiu (IEEE J. Solid State Circuits, 2010)

A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling. - Richard Tseng; Hao Li 001; Dae Hyun Kwon; Yun Chiu; Ada S. Y. Poon (IEEE J. Solid State Circuits, 2010)

Digitally enhanced CMOS RF transmitter with integrated power amplifier - Dae Hyun Kwon (2010)

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation. - Joung-Wook Moon; Sung-Geun Kim; Dae Hyun Kwon; Woo-Young Choi (CICC, 2014)

A clock and data recovery circuit with programmable multi-level phase detector characteristics and a built-in jitter monitor. - Dae Hyun Kwon; Young-Seok Park; Woo-Young Choi (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. - Ki-Hyun Pyun; Dae Hyun Kwon; Woo-Young Choi (APCCAS, 2016)

A 5-8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization. - Sung-Geun Kim; Tongsung Kim; Dae Hyun Kwon; Woo-Young Choi (A-SSCC, 2016)

A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS. - Siddharth Seth; Dae Hyun Kwon; Sriramkumar Venugopalan; Sang Won Son; Yongrong Zuo; Venumadhav Bhagavatula; Jaehyun Lim; Dongjin Oh; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2016)

A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO. - Sung-Geun Kim; Jinsoo Rhim; Dae Hyun Kwon; Min-Hyeong Kim; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS. - Venumadhav Bhagavatula; Dae Hyun Kwon; Jaehun Lee; Quang-Diep Bui; Jeong-Hyun Choi; Siuchuang-Ivan Lu; Sang Won Son (ISSCC, 2017)

A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS. - Qing Liu; Dae Hyun Kwon; Quang-Diep Bui; Jeong-Hyun Choi; Jaehun Lee; Sanghyun Baek; Seungchan Heo; Thomas Byunghak Cho (ISSCC, 2018)

A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector. - Dae Hyun Kwon; Minkyu Kim 003; Sung-Geun Kim; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Low-Power 40-Gb/s Pre-Emphasis PAM-4 Transmitter With Toggling Serializers. - Dae Hyun Kwon; Minkyu Kim 003; Sung-Geun Kim; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Low-Power 28-Gb/s PAM-4MZM Driver With Level Pre-Distortion. - Minkyu Kim 003; Dae Hyun Kwon; Daewon Rho; Woo-Young Choi (IEEE Trans. Circuits Syst. II Express Briefs, 2021)