Chip-package hybrid clock distribution network and DLL for low jitter clock delivery. - Daehyun Chung; Chunghyun Ryu; Hyungsoo Kim; Choonheung Lee; Jinhan Kim; Kicheol Bae; Jiheon Yu; Hoi-Jun Yoo; Joungho Kim (IEEE J. Solid State Circuits, 2006)

Electrical modeling of Through Silicon and Package Vias. - Tapobrata Bandyopadhyay; Ritwik Chatterjee; Daehyun Chung; Madhavan Swaminathan; Rao R. Tummala (3DIC, 2009)

Electrical-thermal co-analysis for power delivery networks in 3D system integration. - Jianyong Xie; Daehyun Chung; Madhavan Swaminathan; Michael McAllister; Alina Deutsch; Lijun Jiang; Barry J. Rubin (3DIC, 2009)