Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. - Taeweon Suh; Daehyun Kim 001; Hsien-Hsin S. Lee (DAC, 2005)

A Characterization of Data Mining Workloads on a Modern Processor. - Amol Ghoting; Gregory Buehrer; Srinivasan Parthasarathy 001; Daehyun Kim 001; Anthony D. Nguyen; Yen-Kuang Chen; Pradeep Dubey (DaMoN, 2005)

Cache-conscious Frequent Pattern Mining on a Modern Processor. - Amol Ghoting; Gregory Buehrer; Srinivasan Parthasarathy 001; Daehyun Kim 001; Anthony D. Nguyen; Yen-Kuang Chen; Pradeep Dubey (VLDB, 2005)

Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures. - Gregory Buehrer; Yen-Kuang Chen; Srinivasan Parthasarathy 001; Anthony D. Nguyen; Amol Ghoting; Daehyun Kim 001 (Memory System Performance and Correctness, 2006)

Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. - Christopher J. Hughes; Radek Grzeszczuk; Eftychios Sifakis; Daehyun Kim 001; Sanjeev Kumar; Andrew Selle; Jatin Chhugani; Matthew J. Holliman; Yen-Kuang Chen (ISCA, 2007)

Scaling performance of interior-point method on large-scale chip multiprocessor system. - Mikhail Smelyanskiy; Victor W. Lee; Daehyun Kim 001; Anthony D. Nguyen; Pradeep Dubey (SC, 2007)

Cache-conscious frequent pattern mining on modern and emerging processors. - Amol Ghoting; Gregory Buehrer; Srinivasan Parthasarathy 001; Daehyun Kim 001; Anthony D. Nguyen; Yen-Kuang Chen; Pradeep Dubey (VLDB J., 2007)

Atomic Vector Operations on Chip Multiprocessors. - Sanjeev Kumar; Daehyun Kim 001; Mikhail Smelyanskiy; Yen-Kuang Chen; Jatin Chhugani; Christopher J. Hughes; Changkyu Kim; Victor W. Lee; Anthony D. Nguyen (ISCA, 2008)

Second Life and the New Generation of Virtual Worlds. - Sanjeev Kumar; Jatin Chhugani; Changkyu Kim; Daehyun Kim 001; Anthony D. Nguyen; Pradeep Dubey; Christian Bienia; Youngmin Kim (Computer, 2008)

Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications. - Yen-Kuang Chen; Jatin Chhugani; Pradeep Dubey; Christopher J. Hughes; Daehyun Kim 001; Sanjeev Kumar; Victor W. Lee; Anthony D. Nguyen; Mikhail Smelyanskiy (Proc. IEEE, 2008)

Mapping High-Fidelity Volume Rendering for Medical Imaging to CPU, GPU and Many-Core Architectures. - Mikhail Smelyanskiy; David R. Holmes III; Jatin Chhugani; Alan Larson; Doug Carmean; Dennis P. Hanson; Pradeep Dubey; Kurt Augustine; Daehyun Kim 001; Alan Kyker; Victor W. Lee; Anthony D. Nguyen; et al. (IEEE Trans. Vis. Comput. Graph., 2009)

Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. - Victor W. Lee; Changkyu Kim; Jatin Chhugani; Michael Deisher; Daehyun Kim 001; Anthony D. Nguyen; Nadathur Satish; Mikhail Smelyanskiy; Srinivas Chennupaty; Per Hammarlund; Ronak Singhal; Pradeep Dubey (ISCA, 2010)

Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. - Nadathur Satish; Changkyu Kim; Jatin Chhugani; Anthony D. Nguyen; Victor W. Lee; Daehyun Kim 001; Pradeep Dubey (SIGMOD Conference, 2010)

Image Processing on Multicore x86 Architectures. - Daehyun Kim 001; Victor W. Lee; Yen-Kuang Chen (IEEE Signal Process. Mag., 2010)

High-Performance 3D Compressive Sensing MRI Reconstruction Using Many-Core Architectures. - Daehyun Kim 001; Joshua Trzasko; Mikhail Smelyanskiy; Clifton Haider; Pradeep Dubey; Armando Manduca (Int. J. Biomed. Imaging, 2011)

Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU. - Dongki Kim; Sungkwang Lee; Jaewoong Chung; Daehyun Kim 001; Dong Hyuk Woo; Sungjoo Yoo; Sunggu Lee (DAC, 2012)

High Performance Non-uniform FFT on Modern X86-based Multi-core Systems. - Dhiraj D. Kalamkar; Joshua D. Trzasko; Srinivas Sridharan 002; Mikhail Smelyanskiy; Daehyun Kim 001; Armando Manduca; Yunhong Shu; Matt A. Bernstein; Bharat Kaul; Pradeep Dubey (IPDPS, 2012)

Tera-scale 1D FFT with low-communication algorithm and Intel® Xeon Phi™ coprocessors. - Jongsoo Park; Ganesh Bikshandi; Karthikeyan Vaidyanathan; Ping Tak Peter Tang; Pradeep Dubey; Daehyun Kim 001 (SC, 2013)

Location-aware cache management for many-core processors with deep cache hierarchy. - Jongsoo Park; Richard M. Yoo; Daya Shanker Khudia; Christopher J. Hughes; Daehyun Kim 001 (SC, 2013)

Efficient backprojection-based synthetic aperture radar computation with many-core processors. - Jongsoo Park; Ping Tak Peter Tang; Mikhail Smelyanskiy; Daehyun Kim 001; Thomas Benson (Sci. Program., 2013)

A framework for low-communication 1-D FFT. - Ping Tak Peter Tang; Jongsoo Park; Daehyun Kim 001; Vladimir Petrov (Sci. Program., 2013)

Improving Communication Performance and Scalability of Native Applications on Intel Xeon Phi Coprocessor Clusters. - Karthikeyan Vaidyanathan; Kiran Pamnany; Dhiraj D. Kalamkar; Alexander Heinecke; Mikhail Smelyanskiy; Jongsoo Park; Daehyun Kim 001; Aniruddha G. Shet; Bharat Kaul; Bálint Joó; Pradeep Dubey (IPDPS, 2014)